From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Jun 2020 14:41:16 +0000 (+0100)
Subject: tracking down what looks like an error in the Simulator Mem ld/st
X-Git-Tag: div_pipeline~391
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61b1e265fb5c8abf5e6f2b17a90cf10fe29c5cc6;p=soc.git

tracking down what looks like an error in the Simulator Mem ld/st
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 532957e8..f76afdab 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -76,9 +76,11 @@ class Mem:
         return val
 
     def st(self, addr, v, width=8):
+        staddr = addr
         remainder = addr & (self.bytes_per_word - 1)
         addr = addr >> self.word_log2
-        print("Writing 0x{:x} to addr 0x{:x}/{:x}".format(v, addr, remainder))
+        print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v,
+                        staddr, addr, remainder))
         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
         if width != self.bytes_per_word:
             if addr in self.mem:
@@ -192,7 +194,7 @@ class ISACaller:
         if initial_mem is None:
             initial_mem = {}
         self.gpr = GPR(decoder2, regfile)
-        self.mem = Mem(initial_mem=initial_mem)
+        self.mem = Mem(bytes_per_word=8, initial_mem=initial_mem)
         self.pc = PC()
         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64) # underlying reg
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 1265ba94..702f8579 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -122,9 +122,10 @@ class TestRunner(FHDLTestCase):
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
         if self.funit == Function.LDST:
             from soc.experiment.l0_cache import TstL0CacheBuffer
-            m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64)
+            m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64,
+                                                    addrwid=4)
             pi = l0.l0.dports[0].pi
-            m.submodules.cu = cu = self.fukls(pi, awid=4)
+            m.submodules.cu = cu = self.fukls(pi, awid=3)
             m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
             m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
         else:
@@ -152,11 +153,20 @@ class TestRunner(FHDLTestCase):
                 # initialise memory
                 if self.funit == Function.LDST:
                     mem = l0.mem.mem
+                    print ("before, init mem", mem.depth, mem.width, mem)
                     for i in range(mem.depth//2):
                         data = sim.mem.ld(i*16, 8)
                         data1 = sim.mem.ld(i*16+8, 8)
+                        print ("init ", i, hex(data), hex(data1))
                         yield mem._array[i].eq(data | (data1<<32))
-                    print ("init mem", mem.depth, mem.width, mem)
+                    yield Settle()
+                    for k, v in sim.mem.mem.items():
+                        print ("    %6x %016x" % (k, v))
+                    print ("before, nmigen mem dump")
+                    for i in range(mem.depth//2):
+                        actual_mem = yield mem._array[i]
+                        print ("    %6i %016x" % (i*2, actual_mem))
+
 
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
@@ -242,7 +252,7 @@ class TestRunner(FHDLTestCase):
                         print ("nmigen mem dump")
                         for i in range(mem.depth//2):
                             actual_mem = yield mem._array[i]
-                            print ("    %6i %032x" % (i*2, actual_mem))
+                            print ("    %6i %016x" % (i*2, actual_mem))
 
                         for i in range(mem.depth//2):
                             data = sim.mem.ld(i*16, 8)
diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
index 3bf7ed60..99ea01b2 100644
--- a/src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -67,12 +67,10 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[1] = 0x0004
         initial_regs[2] = 0x0008
-        initial_mem = {0x0000: (0x12345678, 8),
-                       0x0008: (0x54321234, 8),
-                       0x0010: (0x87654321, 8),
-                       0x0018: (0xabcdef01, 8),
-                       0x0040: (0x22324252, 8),
-                       0x0048: (0x18283848, 8)}
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0010: (0xabcdef0187654321, 8),
+                       0x0040: (0x1828384822324252, 8),
+                        }
         self.run_tst_program(Program(lst), initial_regs,
                              initial_mem=initial_mem)
 
@@ -85,12 +83,10 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[1] = 0x0004
         initial_regs[2] = 0x0008
         initial_regs[3] = 0x00ee
-        initial_mem = {0x0000: (0x12345678, 8),
-                       0x0008: (0x54321234, 8),
-                       0x0010: (0x87654321, 8),
-                       0x0018: (0xabcdef01, 8),
-                       0x0040: (0x22324252, 8),
-                       0x0048: (0x18283848, 8)}
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0010: (0xabcdef0187654321, 8),
+                       0x0040: (0x1828384822324252, 8),
+                        }
         self.run_tst_program(Program(lst), initial_regs,
                              initial_mem=initial_mem)
 
@@ -101,12 +97,10 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[1] = 0x0004
         initial_regs[2] = 0x0002
         initial_regs[3] = 0x15eb
-        initial_mem = {0x0000: (0x12345678, 8),
-                       0x0008: (0x54321234, 8),
-                       0x0010: (0x87654321, 8),
-                       0x0018: (0xabcdef01, 8),
-                       0x0040: (0x22324252, 8),
-                       0x0048: (0x18283848, 8)}
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0010: (0xabcdef0187654321, 8),
+                       0x0040: (0x1828384822324252, 8),
+                        }
         self.run_tst_program(Program(lst), initial_regs,
                              initial_mem=initial_mem)