From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 18 Feb 2019 21:32:20 +0000 (+0000)
Subject: whoops, off-by-one in use of mw, in multiply_1 stage
X-Git-Tag: ls180-24jan2020~1878
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61b2d414a758e3ba146988f197311e510a1c1b97;p=ieee754fpu.git

whoops, off-by-one in use of mw, in multiply_1 stage
---

diff --git a/src/add/fmul.py b/src/add/fmul.py
index bb508e1a..d7466fc3 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -106,9 +106,9 @@ class FPMUL(FPBase):
                 mw = z.m_width
                 m.next = "normalise_1"
                 m.d.sync += [
-                z.m.eq(product[mw+3:]),
-                of.guard.eq(product[mw+2]),
-                of.round_bit.eq(product[mw+1]),
+                z.m.eq(product[mw+2:]),
+                of.guard.eq(product[mw+1]),
+                of.round_bit.eq(product[mw]),
                 of.sticky.eq(product[0:mw] != 0)
             ]