From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 Dec 2021 13:08:53 +0000 (+0000)
Subject: fix up pr/dr/sf in PortInterfaceBase
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61b4a4a6115ae72631a9b86ad0cbef7ee3b75060;p=soc.git

fix up pr/dr/sf in PortInterfaceBase
---

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 58f6c4e8..52605a14 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -225,8 +225,8 @@ class PortInterfaceBase(Elaboratable):
         # TODO: construct an MSRspec here and pass it over in
         # self.set_rd_addr and set_wr_addr below rather than just pr
         pr = ~pi.priv_mode
-        dr = pi.virt_mode   # not yet used
-        sf = pi.mode_32bit   # not yet used
+        dr = pi.virt_mode
+        sf = ~pi.mode_32bit
         msr = MSRSpec(pr=pr, dr=dr, sf=sf)
 
         # detect busy "edge"