From: Nina Engelhardt <nina.engelhardt@omnium-gatherum.de>
Date: Fri, 26 Jul 2013 13:48:25 +0000 (+0200)
Subject: fix synthesis translate on/off switch
X-Git-Tag: 24jan2021_ls180~2099^2~499
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61b8958953eb062e08a1c6994b255c1f79c57dd8;p=litex.git

fix synthesis translate on/off switch
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index f608338c..67402754 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -169,8 +169,8 @@ def _printcomb(f, ns, display_run):
 	if f.comb:
 		# Generate a dummy event to get the simulator
 		# to run the combinatorial process once at the beginning.
-		syn_off = "// synthesis translate off\n"
-		syn_on = "// synthesis translate on\n"
+		syn_off = "// synthesis translate_off\n"
+		syn_on = "// synthesis translate_on\n"
 		dummy_s = Signal(name_override="dummy_s")
 		r += syn_off
 		r += "reg " + _printsig(ns, dummy_s) + ";\n"