From: Chander Sudanthi Date: Thu, 1 Dec 2011 08:15:22 +0000 (-0800) Subject: O3: Remove hardcoded tgts_per_mshr in O3CPU.py. X-Git-Tag: stable_2012_02_02~11 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61c14da751ae80e8c19e0b63ddd629c4152f1c72;p=gem5.git O3: Remove hardcoded tgts_per_mshr in O3CPU.py. There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b --- diff --git a/configs/common/Caches.py b/configs/common/Caches.py index ffcd63c49..0be8001d7 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -33,7 +33,7 @@ class L1Cache(BaseCache): block_size = 64 latency = '1ns' mshrs = 10 - tgts_per_mshr = 5 + tgts_per_mshr = 20 is_top_level = True class L2Cache(BaseCache): diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 47b18a3ec..2a5b6782f 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -146,7 +146,3 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): - BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc) - self.icache.tgts_per_mshr = 20 - self.dcache.tgts_per_mshr = 20 diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 35811282c..9f7c89c7b 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -38,7 +38,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index d4a69d94a..fec21c177 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -39,6 +39,7 @@ class MyCache(BaseCache): class MyL1Cache(MyCache): is_top_level = True + tgts_per_mshr = 20 cpu = DerivO3CPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index a4489f192..c697e97a9 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -42,7 +42,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py index 1718a76e8..489b5c5b6 100644 --- a/tests/configs/realview-o3-dual.py +++ b/tests/configs/realview-o3-dual.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 89f320c04..61e7591e6 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index 125e228a7..786452a09 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py index 13212d5d9..8a003dad8 100644 --- a/tests/configs/tsunami-o3.py +++ b/tests/configs/tsunami-o3.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ----------------------