From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 20:24:54 +0000 (-0700)
Subject: Remove write_verilog call
X-Git-Tag: working-ls180~1208^2~333
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61ca83e099ce9b08b0dcbfaac65a2e2870d58413;p=yosys.git

Remove write_verilog call
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index bd7347a19..99ca4f8d5 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -630,7 +630,7 @@ struct XAigerWriter
 				RTLIL::Selection& sel = holes_module->design->selection_stack.back();
 				sel.select(holes_module);
 
-				Pass::call(holes_module->design, "flatten; aigmap; write_verilog -noexpr -norename holes.v");
+				Pass::call(holes_module->design, "flatten; aigmap");
 
 				holes_module->design->selection_stack.pop_back();