From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Dec 2021 15:27:20 +0000 (+0000)
Subject: move microwatt mmu.bin test 3 page table to test pagetables module
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61d9f44481e8d8595f62a305152d922be99d34b4;p=soc.git

move microwatt mmu.bin test 3 page table to test pagetables module
---

diff --git a/src/soc/experiment/test/pagetables.py b/src/soc/experiment/test/pagetables.py
index 46b4f833..42a75850 100644
--- a/src/soc/experiment/test/pagetables.py
+++ b/src/soc/experiment/test/pagetables.py
@@ -24,6 +24,7 @@ test1 = {
 
 }
 
+
 # executable permission is barred here (EAA=0x2)
 test2 = {
            0x10000:    # PARTITION_TABLE_2
@@ -46,3 +47,12 @@ test2 = {
            #0x10004: 0
 
 }
+
+
+# microwatt mmu.bin first part of test 3. PRTBL must be set to 0x12000, PID to 1
+microwatt_test3 = {
+             0x10000: 0x0930010000000080, # leaf node
+             0x12010: 0x0a00010000000000, # page table
+             0x8108: 0x0000000badc0ffee,  # memory to be looked up
+            }
+
diff --git a/src/soc/simple/test/test_issuer_mmu_microwatt.py b/src/soc/simple/test/test_issuer_mmu_microwatt.py
index 72e6de76..c13529ab 100644
--- a/src/soc/simple/test/test_issuer_mmu_microwatt.py
+++ b/src/soc/simple/test/test_issuer_mmu_microwatt.py
@@ -27,6 +27,8 @@ from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
 from openpower.test.ldst.ldst_cases import LDSTTestCase
 from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
+from soc.experiment.test import pagetables
+
 
 from openpower.simulator.program import Program
 from openpower.endian import bigendian
@@ -48,12 +50,8 @@ class MMUTestCase(TestAccumulatorBase):
         initial_regs = [0] * 32
         initial_regs[2] = 0x124108
 
-        # no pre-loaded memory here
-        initial_mem = {
-             0x12010: 0x0a00010000000000,
-             0x10000: 0x0930010000000080,
-             0x8108: 0x0000000badc0ffee,
-        }
+        # memory same as microwatt test
+        initial_mem = pagetables.microwatt_test3
 
         # set virtual and non-privileged
         # msr: 8000000000000011
@@ -74,13 +72,6 @@ class MMUTestCase(TestAccumulatorBase):
                              initial_msr=initial_msr)
 
 
-
-mmu_test3 = {
-             0x12010: 0x0a00010000000000,
-             0x10000: 0x0930010000000080,
-             0x8108: 0x0000000badc0ffee,
-            }
-
 if __name__ == "__main__":
     svp64 = True
     if len(sys.argv) == 2:
@@ -96,7 +87,7 @@ if __name__ == "__main__":
     # MMU/DCache integration tests
     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
                               microwatt_mmu=True,
-                              rom=mmu_test3))
+                              rom=pagetables.microwatt_test3))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)