From: Luke Kenneth Casson Leighton Date: Sat, 27 Jan 2024 11:14:38 +0000 (+0000) Subject: bug 10344: had to move crfternlogi to TLI-Form X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61e3ef7e;p=openpower-isa.git bug 10344: had to move crfternlogi to TLI-Form --- diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn index ae11d534..1b58fc8e 100644 --- a/openpower/isa/bitmanip.mdwn +++ b/openpower/isa/bitmanip.mdwn @@ -157,8 +157,6 @@ X-Form Pseudo-code: - a <- CR[BT+32] - b <- CR[BA] lut <- CR[4*BFB+32:4*BFB+35] idx <- CR[BT+32] || CR[BA+32] CR[BT+32] <- lut[3-idx] diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index b5b263e8..d1944212 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -346,6 +346,7 @@ |0 |6 |11 |16 |21 |29 |31 | | PO | RT | RA | RB | TLI | XO |Rc | | PO | RT | RA | RB | TLI | XO |L | + | PO | BT | BA | BB | TLI | XO |/ | # 1.6.38 MM-FORM |0 |6 |11 |16 |21 |24 |25 |31 | @@ -386,11 +387,11 @@ BA (11:15) Field used to specify a bit in the CR to be used as a source. - Formats: XL, X + Formats: XL, X, TLI BB (16:20) Field used to specify a bit in the CR to be used as a source. - Formats: XL + Formats: XL, TLI BC (21:25) Field used to specify a bit in the CR to be used as a source. @@ -447,7 +448,7 @@ BT (6:10) Field used to specify a bit in the CR or in the FPSCR to be used as a target. - Formats: XL, X + Formats: XL, X, TLI BX,B (30,16:20) Fields that are concatenated to specify a VSR to be used as a source. diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv index bb110567..1f8ba13f 100644 --- a/openpower/isatables/minor_5.csv +++ b/openpower/isatables/minor_5.csv @@ -1,7 +1,11 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 +# ternlog (integer, CR and CR field) --------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg ---------010,CR,OP_CRFTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg -------00100,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg -------01100,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg -------10100,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg +-----00001-,CR,OP_CRFTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg +-----00101-,CR,OP_CRTERNLOG,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg + +# integer butterfly +-----100100,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg +-----101100,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg +-----110100,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/insndb/asm.py b/src/openpower/insndb/asm.py index 8f6ad336..9797a1e5 100644 --- a/src/openpower/insndb/asm.py +++ b/src/openpower/insndb/asm.py @@ -313,7 +313,9 @@ if __name__ == '__main__': #"sv.cmp/ff=gt *0,*1,*2,0", #"dsld 5,4,5,3", "crfbinlog 3,4,5,15", - #"crbinlog 3,4,5", + "crbinlog 3,4,5", + "crfternlogi 3,4,5,149,5", + "crternlogi 3,4,5,149", ] isa = SVP64Asm(lst, macros=macros) log("list:\n", "\n\t".join(list(isa))) diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py index eacdfeb8..5df82a7f 100644 --- a/src/openpower/test/bitmanip/bitmanip_cases.py +++ b/src/openpower/test/bitmanip/bitmanip_cases.py @@ -48,6 +48,20 @@ def ternlogi(rc, rt, ra, rb, imm): return expected +def crfternlogi(bf, bfa, bfb, imm, mask): + expected = bf&~mask # start at BF, mask overwrites masked bits only + checks = (bfb, bfa, bf) # LUT positions 1<<0=bfb 1<<1=bfa 1<<2=bf + for i in range(4): + lut_index = 0 + for j, check in enumerate(checks): + if check & (1<> i) & 0b1 + if (imm & (1<> i) & 0b1 - if (imm & (1<