From: lkcl Date: Fri, 7 Oct 2022 23:09:47 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~140 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61e54036e77cc1aad42dc479d830403fd0ad83cd;p=libreriscv.git --- diff --git a/openpower/sv/discussion.mdwn b/openpower/sv/discussion.mdwn index 40883cbfe..de29479fc 100644 --- a/openpower/sv/discussion.mdwn +++ b/openpower/sv/discussion.mdwn @@ -9,3 +9,22 @@ check-for-ASCII. I think this is it: https://arxiv.org/pdf/2010.03090.pdf + +# Book start + +Chapter 8. Simple-V Facility +Section 8.1 Introduction: The Simple-V facility (abbreviated as SV) provides a way for a programmer to specify that an instruction, or a sequence of instructions, are to be repeatedly executed using successive register operands. It also provides controls to enable individual iterations to be skipped, to address larger sets of general and floating-point registers, to process registers as arrays of smaller elements, and to specify that arithmetic operations should generate saturated values in case of overflow. ...etc... {Describe the facility and what you can do with it at a mid to high level; don't include rationale for design decisions or warnings about possible alternative designs. Don't waste space inveighing against SIMD, etc.} + +Section 8.2 Simple-V Facility Registers +8.2.1 Expanded GPR register set +8.2.2 Expanded FPR register set +8.3.3 Expanded CR register set +8.3.4 Simple-V SPRs (SVSTATE, SVLR) {Description of SVSRR0 etc. would go in new sections in Book III} + +Section 8.3 Simple-V Instruction Encoding +8.3.1 Introduction {Describe use of prefix instruction word, which instructions can be vectorized, etc} +8.3.2 Simple-V prefix encoding details + +Section 8.4 Simple-V Execution Model + +Section 8.5 Simple-V Instruction Descriptions {setvl etc.}