From: Richard Sandiford <richard.sandiford@arm.com>
Date: Wed, 7 Aug 2019 19:12:15 +0000 (+0000)
Subject: [AArch64] Prefer FPRs over GPRs for INSR
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61ee25b9e7d84fbb18218887d1fecfb10f72993a;p=gcc.git

[AArch64] Prefer FPRs over GPRs for INSR

INSR of GPRs involves a cross-file move while INSR of FPRs doesn't.
We should therefore disparage the GPR version relative to the FPR
version.

The patch also adds MOVPRFX handling, but this is only tested
properly by the ACLE.

2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (vec_shl_insert_<mode>): Add
	MOVPRFX alternatives.  Make the GPR alternatives more expensive
	than the FPR ones.

gcc/testsuite/
	* gcc.target/aarch64/sve/init_12.c: Expect w1 to be moved into
	a temporary FPR.

From-SVN: r274192
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 31cbd59c4b6..ef6c201e29f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-sve.md (vec_shl_insert_<mode>): Add
+	MOVPRFX alternatives.  Make the GPR alternatives more expensive
+	than the FPR ones.
+
 2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* config/aarch64/aarch64-sve.md (fold_extract_last_<mode>):
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 41c92a01bab..baba7318f20 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -835,15 +835,18 @@
 
 ;; Shift an SVE vector left and insert a scalar into element 0.
 (define_insn "vec_shl_insert_<mode>"
-  [(set (match_operand:SVE_ALL 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_ALL 0 "register_operand" "=?w, w, ??&w, ?&w")
 	(unspec:SVE_ALL
-	  [(match_operand:SVE_ALL 1 "register_operand" "0, 0")
-	   (match_operand:<VEL> 2 "register_operand" "rZ, w")]
+	  [(match_operand:SVE_ALL 1 "register_operand" "0, 0, w, w")
+	   (match_operand:<VEL> 2 "aarch64_reg_or_zero" "rZ, w, rZ, w")]
 	  UNSPEC_INSR))]
   "TARGET_SVE"
   "@
    insr\t%0.<Vetype>, %<vwcore>2
-   insr\t%0.<Vetype>, %<Vetype>2"
+   insr\t%0.<Vetype>, %<Vetype>2
+   movprfx\t%0, %1\;insr\t%0.<Vetype>, %<vwcore>2
+   movprfx\t%0, %1\;insr\t%0.<Vetype>, %<Vetype>2"
+  [(set_attr "movprfx" "*,*,yes,yes")]
 )
 
 ;; -------------------------------------------------------------------------
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dd37b72aeda..22cf0e97c12 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sve/init_12.c: Expect w1 to be moved into
+	a temporary FPR.
+
 2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* gcc.target/aarch64/sve/clastb_8.c: New test.
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_12.c b/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
index cbf418e4e63..bc698ddd38d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
@@ -10,12 +10,13 @@ typedef int32_t vnx4si __attribute__((vector_size (32)));
 
 /*
 ** foo:
+**	fmov	(s[0-9]+), w1
 **	mov	(z[0-9]+\.s), w2
 **	mov	(z[0-9]+\.s), w0
-**	insr	\2, w1
-**	insr	\2, w1
-**	insr	\2, w1
-**	zip1	\2, \2, \1
+**	insr	\3, \1
+**	insr	\3, \1
+**	insr	\3, \1
+**	zip1	\3, \3, \2
 **	...
 */
 __attribute__((noipa))