From: Ulrich Weigand <uweigand@de.ibm.com>
Date: Thu, 15 Aug 2002 09:55:31 +0000 (+0000)
Subject: s390.c (legitimize_address): Optimize loading of large displacements.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61f02ff548608d1fe98c35f724575cb87865946b;p=gcc.git

s390.c (legitimize_address): Optimize loading of large displacements.

	* config/s390/s390.c (legitimize_address): Optimize loading
	of large displacements.

From-SVN: r56345
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ab35fcff585..71ae78dae20 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-08-15  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* config/s390/s390.c (legitimize_address): Optimize loading
+	of large displacements.
+
 2002-08-14  Douglas B Rupp  <rupp@gnat.com>
 
 	* config/alpha/alpha-protos.h: Update.
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 6a29b764f00..85952c5bacb 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2084,6 +2084,31 @@ legitimize_address (x, oldx, mode)
 
   x = eliminate_constant_term (x, &constant_term);
 
+  /* Optimize loading of large displacements by splitting them
+     into the multiple of 4K and the rest; this allows the
+     former to be CSE'd if possible. 
+
+     Don't do this if the displacement is added to a register
+     pointing into the stack frame, as the offsets will
+     change later anyway.  */
+
+  if (GET_CODE (constant_term) == CONST_INT
+      && (INTVAL (constant_term) < 0
+          || INTVAL (constant_term) >= 4096)
+      && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
+    {
+      HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
+      HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
+
+      rtx temp = gen_reg_rtx (Pmode);
+      rtx val  = force_operand (GEN_INT (upper), temp);
+      if (val != temp)
+	emit_move_insn (temp, val);
+
+      x = gen_rtx_PLUS (Pmode, x, temp);
+      constant_term = GEN_INT (lower);
+    }
+
   if (GET_CODE (x) == PLUS)
     {
       if (GET_CODE (XEXP (x, 0)) == REG)