From: Sandipan Das <sandipan@linux.vnet.ibm.com>
Date: Thu, 7 Jun 2018 05:41:11 +0000 (+0530)
Subject: arch-power: Add fixed-point word arithmetic modulo instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=61f794885fa7bd0cac9c2874b9d0e935d3d06908;p=gem5.git

arch-power: Add fixed-point word arithmetic modulo instructions

This adds the following arithmetic instructions:
  * Modulo Signed Word (modsw)
  * Modulo Unsigned Word (moduw)

Change-Id: I5590e569afb71dd429c473bd18c65457e2c49286
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 8b8b2c7c1..210f2aea1 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -380,6 +380,28 @@ decode PO default Unknown::unknown() {
             181: stdux({{ Mem = Rs; }});
         }
 
+        format IntArithOp {
+            779: modsw({{
+                int64_t src1 = Ra_sw;
+                int64_t src2 = Rb_sw;
+                if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
+                    Rt = src1 % src2;
+                } else {
+                    Rt = 0;
+                }
+            }});
+
+            267: moduw({{
+                uint64_t src1 = Ra_uw;
+                uint64_t src2 = Rb_uw;
+                if (src2 != 0) {
+                    Rt = src1 % src2;
+                } else {
+                    Rt = 0;
+                }
+            }});
+        }
+
         format IntOp {
             0: cmp({{
                 Xer xer = XER;
@@ -561,7 +583,7 @@ decode PO default Unknown::unknown() {
 
             // Arithmetic instructions all use source registers Ra and Rb,
             // with destination register Rt.
-            format IntArithOp {
+            format IntArithCheckRcOp {
                 75: mulhw({{
                     uint64_t res = (int64_t)Ra_sw * Rb_sw;
                     res = res >> 32;
diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa
index a21deab56..9bbd65e70 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -324,6 +324,17 @@ def format IntSumOp(src1, src2, ca = {{ 0 }}, computeCA = 0,
 }};
 
 
+// Instructions that use source registers Ra and Rb, with the result
+// placed into Rt but do not check for carry, overflow or the Rc bit.
+def format IntArithOp(code, inst_flags = []) {{
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenAluOp(name, Name, 'IntArithOp', code, inst_flags, BasicDecode,
+                 BasicConstructor)
+}};
+
+
 // Instructions that use source registers Ra and Rb, with the result
 // placed into Rt. Basically multiply and divide instructions. The
 // carry bit is never set, but overflow can be calculated. In certain
@@ -334,7 +345,7 @@ def format IntSumOp(src1, src2, ca = {{ 0 }}, computeCA = 0,
 // each instruction to deal with different combinations of having the
 // OE bit set or unset and the Rc bit set or unset too. Otherwise, we
 // generate two versions of each instruction to deal with the Rc bit.
-def format IntArithOp(code, computeOV = 0, inst_flags = []) {{
+def format IntArithCheckRcOp(code, computeOV = 0, inst_flags = []) {{
 
     # The result is always in Rt, but the source values vary
     dict = {'result':'Rt', 'inputa':'src1', 'inputb':'src2'}