From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Thu, 2 May 2019 15:44:39 +0000 (+0200)
Subject: radv: only need to force emit the TCS regs on Vega10 and Raven1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=62001f3dff8957005f15bd6401c917abf6cec321;p=mesa.git

radv: only need to force emit the TCS regs on Vega10 and Raven1

Other GFX9 chips aren't affected.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index b4a19aa2e5d..796d78e34f4 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3690,8 +3690,8 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
 	if (shader_count >= 2)
 		ac_init_exec_full_mask(&ctx.ac);
 
-	if (ctx.ac.chip_class == GFX9 &&
-	    ctx.ac.family != CHIP_VEGA20 &&
+	if ((ctx.ac.family == CHIP_VEGA10 ||
+	     ctx.ac.family == CHIP_RAVEN) &&
 	    shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
 		ac_nir_fixup_ls_hs_input_vgprs(&ctx);