From: lkcl <lkcl@web>
Date: Thu, 21 Apr 2022 11:49:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2653
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=620a97ab2fc2b89baa072fe25a4264f9904864ab;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index cbb061ab8..c98cdb8a3 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -20,15 +20,15 @@ big-integer add due to the rules set in SVP64 that all Vector Operations
 are directly equivalent to the strict Program Order Execution of
 their element-level operations.
 
-    R0,CA = A0+B0+CA
+    R0,CA = A0+B0+CA  adde r0,a0,b0
         |
         +----------+
                    |
-    R1,CA = A1+B1+CA
+    R1,CA = A1+B1+CA  adde r1,a1,b1
         |
         +----------+
                    |
-    R2,CA = A2+B2+CA
+    R2,CA = A2+B2+CA  adde r2,a2,b2
 
 Thus, due to sequential execution of `adde` both consuming and producing
 a CA Flag, `sv.adde` is in effect an alias for Vectorised add.  As such,