From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Nov 2013 16:58:05 +0000 (+0100)
Subject: Updated TODOs
X-Git-Tag: yosys-0.2.0~311
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=620b7c900a851526339c265ba6ea9510530de985;p=yosys.git

Updated TODOs
---

diff --git a/README b/README
index 2277ef129..940689689 100644
--- a/README
+++ b/README
@@ -296,8 +296,7 @@ Roadmap / Large-scale TODOs
    - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
 
 - Technology mapping for real-world applications
-   - Add "mini synth script" feature to techmap pass
-   - Add const-folding via cell parameters to techmap pass
+   - Add bit-wise const-folding via cell parameters to techmap pass
    - Rewrite current stdcells.v techmap rules (modular and clean)
    - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)