From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 30 Dec 2017 17:41:49 +0000 (+0100)
Subject: soc/integration/soc_core: avoid removing uart interrupts (break some designs)
X-Git-Tag: 24jan2021_ls180~1773
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=621aaf6988f4c7b047b165f27935c160eda319e1;p=litex.git

soc/integration/soc_core: avoid removing uart interrupts (break some designs)
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 0a9c98b6..e2dd457f 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -145,8 +145,8 @@ class SoCCore(Module):
             else:
                 self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
                 self.submodules.uart = uart.UART(self.uart_phy)
-        else:
-            del self.soc_interrupt_map["uart"]
+        #else:
+        #    del self.soc_interrupt_map["uart"]
 
         if ident:
             if ident_version: