From: Luke Kenneth Casson Leighton Date: Sun, 15 Mar 2020 20:05:45 +0000 (+0000) Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6220203afdc58da6b7e51f38f122a4cce8f62cba;p=libre-riscv-dev.git Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility --- diff --git a/39/07f79163f132c2c621981ec7c9f2d84b17248f b/39/07f79163f132c2c621981ec7c9f2d84b17248f new file mode 100644 index 0000000..3b89c89 --- /dev/null +++ b/39/07f79163f132c2c621981ec7c9f2d84b17248f @@ -0,0 +1,79 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Sun, 15 Mar 2020 20:06:20 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jDZWd-0000iQ-DN; Sun, 15 Mar 2020 20:06:19 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jDZWb-0000iK-V7 + for libre-riscv-dev@lists.libre-riscv.org; Sun, 15 Mar 2020 20:06:17 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lkcl.net; + s=201607131; + h=Content-Type:To:Subject:Message-ID:Date:From:In-Reply-To:References:MIME-Version; + bh=aqS806wgmNlgwn+mI7RpxqO11AkpxpKUsUNmStGXRK0=; + b=MgRsXD8FW7pLFrqI7OBMKUUVa3n5249pmYAHTARTNCTTbcq75uhY+04HBRyh8kuY7Nb4MUIJQsTQUO0wn7iHsROPfRvTBVLPOA26BlEE4eoGCqKdB81B+1wq+fVklK6DzzV1eMt3L1WfMXD1HSGRNDwpnYKF4V8I4tF9ef4CQ48=; +Received: from mail-lf1-f54.google.com ([209.85.167.54]) + by lkcl.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.84_2) (envelope-from ) id 1jDZWb-0008B3-KZ + for libre-riscv-dev@lists.libre-riscv.org; Sun, 15 Mar 2020 20:06:17 +0000 +Received: by mail-lf1-f54.google.com with SMTP id b186so12084722lfg.11 + for ; + Sun, 15 Mar 2020 13:06:02 -0700 (PDT) +X-Gm-Message-State: ANhLgQ0RFtsjpIAhSYftTXk67ZBBBWzGbIR6Mj97CkcN0AdkjmwMWN2s + ptBqVRPHzTwTGdicG8vl8eGIDHhfSRGR1Hv6qQM= +X-Google-Smtp-Source: ADFU+vshWQXPNmy7Bvbn41Reroe78xVRxMxRAX4BCt/Hb6OZgKbC+QFdWfQt4iYZpVmhg3IRXIbcDY4FX2KjeLYpcmY= +X-Received: by 2002:a19:4cc4:: with SMTP id z187mr14472962lfa.49.1584302756693; + Sun, 15 Mar 2020 13:05:56 -0700 (PDT) +MIME-Version: 1.0 +References: <6AC4EFD4-AA30-42C7-855A-CE68A62F107F@gatech.edu> + + <20200315051018.svaw4aor7ifwn725@topoi.pooq.com> + + + + <1BB9EA49-275B-4365-963E-9FC21D574BB7@gatech.edu> + <16F24775-E25B-4E31-A1D4-145EB65FB1D8@gatech.edu> + + <75CA4609-370F-455E-A88D-50E3766D45D7@gatech.edu> + + <884F8FEE-60FF-4580-A2E7-8AAA40A6DB6B@gatech.edu> + + <8C348DCE-274B-476B-8F61-C1BB5F1C3EC1@gatech.edu> + + <7E1C43EE-2E5C-4CD5-8711-54404C19CFA8@gatech.edu> +In-Reply-To: <7E1C43EE-2E5C-4CD5-8711-54404C19CFA8@gatech.edu> +From: Luke Kenneth Casson Leighton +Date: Sun, 15 Mar 2020 20:05:45 +0000 +X-Gmail-Original-Message-ID: +Message-ID: +To: Libre-RISCV General Development +Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture + feasibility +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +T24gU3VuLCBNYXIgMTUsIDIwMjAgYXQgODowMCBQTSBJbW1hbnVlbCwgWWVob3dzaHVhIFUKPHlp +bW1hbnVlbDNAZ2F0ZWNoLmVkdT4gd3JvdGU6Cj4KPiA+IHg4NiBhbmQgeDg2XzY0IHVzZXItbW9k +ZSBzaW5jZSB0aGUgcGF0ZW50cyBmb3IgdGhlIGJhc2UgSVNBIHdpbGwgaGF2ZQo+ID4gZXhwaXJl +ZCBieSB0aGVuCj4KPiBEaWQgeW91IGhlYXIgVEhBVCBpbnRlbD8KCmhhaGEgOikKCl9fX19fX19f +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpYnJlLXJpc2N2LWRldiBt +YWlsaW5nIGxpc3QKbGlicmUtcmlzY3YtZGV2QGxpc3RzLmxpYnJlLXJpc2N2Lm9yZwpodHRwOi8v +bGlzdHMubGlicmUtcmlzY3Yub3JnL21haWxtYW4vbGlzdGluZm8vbGlicmUtcmlzY3YtZGV2Cg==