From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Wed, 27 May 2020 07:58:10 +0000 (+0000)
Subject: printattrs: Add test.
X-Git-Tag: working-ls180~528^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6228b10c9f354afaa009491b061583e8a686fbd8;p=yosys.git

printattrs: Add test.
---

diff --git a/tests/various/printattr.ys b/tests/various/printattr.ys
new file mode 100644
index 000000000..afc6d8eb6
--- /dev/null
+++ b/tests/various/printattr.ys
@@ -0,0 +1,14 @@
+logger -expect log ".*cells_not_processed=[01]* .*" 1
+logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+read_verilog <<EOT
+module mux2(a, b, s, y);
+	input a, b, s;
+	output y;
+
+	wire s_n = ~s;
+	wire t0 = s & a;
+	wire t1 = s_n & b;
+	assign y = t0 | t1;
+endmodule
+EOT
+printattrs