From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 28 Jan 2015 21:49:49 +0000 (+0100)
Subject: mac: use eth_phy_description inside mac
X-Git-Tag: 24jan2021_ls180~2604^2~115
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6249209f941a071aef99cbba4b69854c8a53c0e9;p=litex.git

mac: use eth_phy_description inside mac
---

diff --git a/liteeth/mac/core/__init__.py b/liteeth/mac/core/__init__.py
index e4c378a8..2967e0b5 100644
--- a/liteeth/mac/core/__init__.py
+++ b/liteeth/mac/core/__init__.py
@@ -29,14 +29,14 @@ class LiteEthMACCore(Module, AutoCSR):
 
 		# Converters
 		reverse = endianness == "be"
-		tx_converter = Converter(eth_mac_description(dw), eth_mac_description(phy.dw), reverse=reverse)
-		rx_converter = Converter(eth_mac_description(phy.dw), eth_mac_description(dw), reverse=reverse)
+		tx_converter = Converter(eth_phy_description(dw), eth_phy_description(phy.dw), reverse=reverse)
+		rx_converter = Converter(eth_phy_description(phy.dw), eth_phy_description(dw), reverse=reverse)
 		self.submodules += RenameClockDomains(tx_converter, "eth_tx")
 		self.submodules += RenameClockDomains(rx_converter, "eth_rx")
 
 		# Cross Domain Crossing
-		tx_cdc = AsyncFIFO(eth_mac_description(dw), 4)
-		rx_cdc = AsyncFIFO(eth_mac_description(dw), 4)
+		tx_cdc = AsyncFIFO(eth_phy_description(dw), 4)
+		rx_cdc = AsyncFIFO(eth_phy_description(dw), 4)
 		self.submodules +=  RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
 		self.submodules +=  RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
 
diff --git a/liteeth/mac/core/last_be.py b/liteeth/mac/core/last_be.py
index deaf7fd7..ce39be2c 100644
--- a/liteeth/mac/core/last_be.py
+++ b/liteeth/mac/core/last_be.py
@@ -3,7 +3,7 @@ from liteeth.mac.common import *
 
 class LiteEthMACTXLastBE(Module):
 	def __init__(self, dw):
-		self.sink = sink = Sink(eth_mac_description(dw))
+		self.sink = sink = Sink(eth_phy_description(dw))
 		self.source = source = Source(eth_phy_description(dw))
 		###
 		ongoing = Signal()
@@ -26,7 +26,7 @@ class LiteEthMACTXLastBE(Module):
 class LiteEthMACRXLastBE(Module):
 	def __init__(self, dw):
 		self.sink = sink = Sink(eth_phy_description(dw))
-		self.source = source = Source(eth_mac_description(dw))
+		self.source = source = Source(eth_phy_description(dw))
 		###
 		self.comb += [
 			source.stb.eq(sink.stb),
diff --git a/liteeth/mac/frontend/sram.py b/liteeth/mac/frontend/sram.py
index 1ddbea29..fcb698ad 100644
--- a/liteeth/mac/frontend/sram.py
+++ b/liteeth/mac/frontend/sram.py
@@ -6,7 +6,7 @@ from migen.bank.eventmanager import *
 
 class LiteEthMACSRAMWriter(Module, AutoCSR):
 	def __init__(self, dw, depth, nslots=2):
-		self.sink = sink = Sink(eth_mac_description(dw))
+		self.sink = sink = Sink(eth_phy_description(dw))
 		self.crc_error = Signal()
 
 		slotbits = max(log2_int(nslots), 1)
@@ -131,7 +131,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
 
 class LiteEthMACSRAMReader(Module, AutoCSR):
 	def __init__(self, dw, depth, nslots=2):
-		self.source = source = Source(eth_mac_description(dw))
+		self.source = source = Source(eth_phy_description(dw))
 
 		slotbits = max(log2_int(nslots), 1)
 		lengthbits = log2_int(depth*4) # length in bytes
diff --git a/liteeth/mac/frontend/wishbone.py b/liteeth/mac/frontend/wishbone.py
index b2baf372..c6cf6718 100644
--- a/liteeth/mac/frontend/wishbone.py
+++ b/liteeth/mac/frontend/wishbone.py
@@ -7,8 +7,8 @@ from migen.fhdl.simplify import FullMemoryWE
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):
 	def __init__(self, dw, nrxslots=2, ntxslots=2):
-		self.sink = Sink(eth_mac_description(dw))
-		self.source = Source(eth_mac_description(dw))
+		self.sink = Sink(eth_phy_description(dw))
+		self.source = Source(eth_phy_description(dw))
 		self.bus = wishbone.Interface()
 		###
 		# storage in SRAM