From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Jul 2020 11:59:19 +0000 (+0100)
Subject: add spr input record
X-Git-Tag: div_pipeline~162^2~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=624b62bda41b49d5eaa06dfdc80871634eb67f8d;p=soc.git

add spr input record
---

diff --git a/src/soc/fu/spr/spr_input_record.py b/src/soc/fu/spr/spr_input_record.py
new file mode 100644
index 00000000..67174376
--- /dev/null
+++ b/src/soc/fu/spr/spr_input_record.py
@@ -0,0 +1,42 @@
+from nmigen.hdl.rec import Record, Layout
+
+from soc.decoder.power_enums import (InternalOp, Function)
+
+
+class CompSPROpSubset(Record):
+    """CompSPROpSubset
+
+    a copy of the relevant subset information from Decode2Execute1Type
+    needed for TRAP operations.  use with eq_from_execute1 (below) to
+    grab subsets.
+    """
+    def __init__(self, name=None):
+        layout = (('insn_type', InternalOp),
+                  ('fn_unit', Function),
+                  ('insn', 32),
+                  ('is_32bit', 1),
+                  )
+
+        Record.__init__(self, Layout(layout), name=name)
+
+        # grrr.  Record does not have kwargs
+        self.insn_type.reset_less = True
+        self.insn.reset_less = True
+        self.fn_unit.reset_less = True
+        self.is_32bit.reset_less = True
+
+    def eq_from_execute1(self, other):
+        """ use this to copy in from Decode2Execute1Type
+        """
+        res = []
+        for fname, sig in self.fields.items():
+            eqfrom = other.fields[fname]
+            res.append(sig.eq(eqfrom))
+        return res
+
+    def ports(self):
+        return [self.insn_type,
+                self.insn,
+                self.fn_unit,
+                self.is_32bit,
+        ]