From: Anton Blanchard Date: Wed, 11 Aug 2021 04:34:41 +0000 (+1000) Subject: Reduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6254bb5ee943e475a2959d1f9a78b2e988f6162c;p=microwatt.git Reduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut We've been investigating why the barrel rotator uses an enormous number of cells on the yosys ECP5 target. Eventually it was narrowed down to the -abc9 -nowidelut options, which see the cell count go from 4985 cells to 841 cells. Using the same options on an Orange Crab build reduces the cell count from 50864 to 36085. The main differences: LUT4 31040 -> 25270 PFUMX 6956 -> 0 L6MUX21 1746 -> 0 CCU2C 2066 -> 1759 Signed-off-by: Anton Blanchard --- diff --git a/Makefile b/Makefile index f57d333..e486a29 100644 --- a/Makefile +++ b/Makefile @@ -196,7 +196,7 @@ fpga_files = fpga/soc_reset.vhdl \ synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) microwatt.json: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"