From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 21 Sep 2019 00:49:26 +0000 (-0700)
Subject: Add testcase
X-Git-Tag: working-ls180~1050^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6258e6a7e28ade2bdc7b6809675461326c873a45;p=yosys.git

Add testcase
---

diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
new file mode 100644
index 000000000..4773d5ce3
--- /dev/null
+++ b/tests/techmap/autopurge.ys
@@ -0,0 +1,43 @@
+# https://github.com/YosysHQ/yosys/issues/1391
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+read_verilog -overwrite <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+wire j;
+sub s0(i, o, j);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy