From: lkcl <lkcl@web>
Date: Thu, 28 Jan 2021 15:58:50 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~270
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=625cd65abc962d440609e6d3ca8983cf46bef57e;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 9cc27bbc1..58a58f22c 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -11,6 +11,7 @@ Links:
   assembler translator
 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
   assembler translator
+* <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming