From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 20 May 2018 11:20:15 +0000 (+0100)
Subject: update slides
X-Git-Tag: convert-csv-opcode-to-binary~5354
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=625e8b964e0043d69d4348101462b647cf3ea406;p=libreriscv.git

update slides
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 9ab313213..f419ffdcc 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -84,6 +84,22 @@
 }
 
 
+\frame{\frametitle{Implementation Options}
+
+ \begin{itemize}
+   \item Absolute minimum: Exceptions (CSRs needed)\vspace{10pt}
+   \item Hardware loop, single-instruction issue\vspace{10pt}
+   \item Hardware loop, parallel (multi-instruction) issue\vspace{10pt}
+   \item Hardware loop, full parallel ALU (not recommended)\vspace{10pt}
+  \end{itemize}
+  Considerations:\vspace{10pt}
+  \begin{itemize}
+   \item OoO may split off 4+ single-instructions at a time\vspace{10pt}
+   \item Minimum VL MUST be sufficient to cover regfile LD/ST\vspace{10pt}
+  \end{itemize}
+}
+
+
 \frame{\frametitle{How are SIMD Instructions Vectorised?}
 
  \begin{itemize}
@@ -99,6 +115,7 @@
   \end{itemize}
 }
 
+
 \frame{\frametitle{What's the deal / juice / score?}
 
  \begin{itemize}
@@ -207,18 +224,6 @@ for (int i = 0; i < VL; ++i)
 \end{frame}
 
 
-\frame{\frametitle{slide}
-
- \begin{itemize}
-   \item \vspace{10pt}
-  \end{itemize}
-  Considerations:\vspace{10pt}
-  \begin{itemize}
-   \item \vspace{10pt}
-  \end{itemize}
-}
-
-
 \frame{\frametitle{Opcodes, compared to RVV}
 
  \begin{itemize}