From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 May 2021 12:01:42 +0000 (+0100)
Subject: classic wishbone mode: must not do ack if already acked
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=626e172f340ce6e26842b13ee90cef6a0f8c22a4;p=soc.git

classic wishbone mode: must not do ack if already acked
---

diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py
index 994f9626..25f2da74 100644
--- a/src/soc/bus/SPBlock512W64B8W.py
+++ b/src/soc/bus/SPBlock512W64B8W.py
@@ -59,7 +59,8 @@ class SPBlock512W64B8W(Elaboratable):
         with m.If(self.enable): # in case of layout problems
             # wishbone is active if cyc and stb set
             wb_active = Signal()
-            m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb)
+            m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb &
+                                     ~self.bus.ack)
 
             # generate ack (no "pipeline" mode here)
             m.d.sync += self.bus.ack.eq(wb_active)