From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Mar 2020 21:38:50 +0000 (-0700)
Subject: opt_expr: add failing $xnor test
X-Git-Tag: working-ls180~708^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6274f0b075abba2af9193e2245eacee5cc66e4c5;p=yosys.git

opt_expr: add failing $xnor test
---

diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys
index a458c9a27..21439fd53 100644
--- a/tests/opt/opt_expr_xor.ys
+++ b/tests/opt/opt_expr_xor.ys
@@ -14,7 +14,7 @@ equiv_opt opt_expr
 design -load postopt
 select -assert-none t:$xor
 select -assert-none t:$xnor
-select -assert-count 2 t:$_NOT_
+select -assert-count 2 t:$not
 
 
 design -load read
@@ -38,3 +38,15 @@ equiv_opt opt_expr
 design -load postopt
 select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
 select -assert-count 1 t:$_NOT_
+
+
+design -reset
+read_verilog <<EOT
+module top(input a, output [1:0] w, x, y, z);
+assign w = a^1'b0;
+assign x = a^1'b1;
+assign y = a~^1'b0;
+assign z = a~^1'b1;
+endmodule
+EOT
+equiv_opt opt_expr