From: Przemyslaw Wirkus Date: Thu, 22 Oct 2020 14:17:35 +0000 (+0100) Subject: [PATCH][GAS][AArch64] Define BRBE system registers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6278c6a66379c40d2d91107a2101408ec4ca0673;p=binutils-gdb.git [PATCH][GAS][AArch64] Define BRBE system registers This patch introduces BRBE (Branch Record Buffer Extension) system registers. Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default). gas/ChangeLog: 2020-10-08 Przemyslaw Wirkus * NEWS: Docs update. * testsuite/gas/aarch64/brbe-invalid.d: New test. * testsuite/gas/aarch64/brbe-invalid.l: New test. * testsuite/gas/aarch64/brbe-invalid.s: New test. * testsuite/gas/aarch64/brbe.d: New test. * testsuite/gas/aarch64/brbe.s: New test. opcodes/ChangeLog: 2020-10-08 Przemyslaw Wirkus * aarch64-opc.c: Add BRBE system registers. --- diff --git a/gas/NEWS b/gas/NEWS index 61a69efa66e..da1189c4c1e 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -15,8 +15,9 @@ Add support for Cortex-R82, Neoverse V1, and Neoverse N2 for ARM. * Add support for ETMv4 (Embedded Trace Macrocell), ETE (Embedded Trace - Extension), TRBE (Trace Buffer Extension) and CSRE (Call Stack Recorder - Extension) system registers for AArch64. + Extension), TRBE (Trace Buffer Extension), CSRE (Call Stack Recorder + Extension) and BRBE (Branch Record Buffer Extension) system registers for + AArch64. * Add support for Armv8-R AArch64. diff --git a/gas/testsuite/gas/aarch64/brbe-invalid.d b/gas/testsuite/gas/aarch64/brbe-invalid.d new file mode 100644 index 00000000000..dc42fc22c60 --- /dev/null +++ b/gas/testsuite/gas/aarch64/brbe-invalid.d @@ -0,0 +1,3 @@ +#name: Invalid BRBE System registers usage +#source: brbe-invalid.s +#warning_output: brbe-invalid.l diff --git a/gas/testsuite/gas/aarch64/brbe-invalid.l b/gas/testsuite/gas/aarch64/brbe-invalid.l new file mode 100644 index 00000000000..2839206629e --- /dev/null +++ b/gas/testsuite/gas/aarch64/brbe-invalid.l @@ -0,0 +1,98 @@ +.*: Assembler messages: +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbidr0_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc0_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc1_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc2_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc3_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc4_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc5_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc6_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc7_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc8_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc9_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc10_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc11_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc12_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc13_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc14_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc15_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc16_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc17_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc18_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc19_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc20_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc21_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc22_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc23_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc24_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc25_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc26_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc27_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc28_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc29_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc30_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbsrc31_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt0_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt1_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt2_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt3_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt4_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt5_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt6_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt7_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt8_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt9_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt10_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt11_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt12_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt13_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt14_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt15_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt16_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt17_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt18_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt19_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt20_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt21_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt22_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt23_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt24_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt25_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt26_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt27_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt28_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt29_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt30_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbtgt31_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf0_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf1_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf2_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf3_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf4_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf5_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf6_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf7_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf8_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf9_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf10_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf11_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf12_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf13_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf14_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf15_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf16_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf17_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf18_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf19_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf20_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf21_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf22_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf23_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf24_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf25_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf26_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf27_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf28_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf29_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf30_el1,x0' +.*: Warning: specified register cannot be written to at operand 1 -- `msr brbinf31_el1,x0' diff --git a/gas/testsuite/gas/aarch64/brbe-invalid.s b/gas/testsuite/gas/aarch64/brbe-invalid.s new file mode 100644 index 00000000000..4f82d889762 --- /dev/null +++ b/gas/testsuite/gas/aarch64/brbe-invalid.s @@ -0,0 +1,99 @@ +/* Write to read-only BRBE system registers. */ + +msr brbidr0_el1, x0 +msr brbsrc0_el1, x0 +msr brbsrc1_el1, x0 +msr brbsrc2_el1, x0 +msr brbsrc3_el1, x0 +msr brbsrc4_el1, x0 +msr brbsrc5_el1, x0 +msr brbsrc6_el1, x0 +msr brbsrc7_el1, x0 +msr brbsrc8_el1, x0 +msr brbsrc9_el1, x0 +msr brbsrc10_el1, x0 +msr brbsrc11_el1, x0 +msr brbsrc12_el1, x0 +msr brbsrc13_el1, x0 +msr brbsrc14_el1, x0 +msr brbsrc15_el1, x0 +msr brbsrc16_el1, x0 +msr brbsrc17_el1, x0 +msr brbsrc18_el1, x0 +msr brbsrc19_el1, x0 +msr brbsrc20_el1, x0 +msr brbsrc21_el1, x0 +msr brbsrc22_el1, x0 +msr brbsrc23_el1, x0 +msr brbsrc24_el1, x0 +msr brbsrc25_el1, x0 +msr brbsrc26_el1, x0 +msr brbsrc27_el1, x0 +msr brbsrc28_el1, x0 +msr brbsrc29_el1, x0 +msr brbsrc30_el1, x0 +msr brbsrc31_el1, x0 +msr brbtgt0_el1, x0 +msr brbtgt1_el1, x0 +msr brbtgt2_el1, x0 +msr brbtgt3_el1, x0 +msr brbtgt4_el1, x0 +msr brbtgt5_el1, x0 +msr brbtgt6_el1, x0 +msr brbtgt7_el1, x0 +msr brbtgt8_el1, x0 +msr brbtgt9_el1, x0 +msr brbtgt10_el1, x0 +msr brbtgt11_el1, x0 +msr brbtgt12_el1, x0 +msr brbtgt13_el1, x0 +msr brbtgt14_el1, x0 +msr brbtgt15_el1, x0 +msr brbtgt16_el1, x0 +msr brbtgt17_el1, x0 +msr brbtgt18_el1, x0 +msr brbtgt19_el1, x0 +msr brbtgt20_el1, x0 +msr brbtgt21_el1, x0 +msr brbtgt22_el1, x0 +msr brbtgt23_el1, x0 +msr brbtgt24_el1, x0 +msr brbtgt25_el1, x0 +msr brbtgt26_el1, x0 +msr brbtgt27_el1, x0 +msr brbtgt28_el1, x0 +msr brbtgt29_el1, x0 +msr brbtgt30_el1, x0 +msr brbtgt31_el1, x0 +msr brbinf0_el1, x0 +msr brbinf1_el1, x0 +msr brbinf2_el1, x0 +msr brbinf3_el1, x0 +msr brbinf4_el1, x0 +msr brbinf5_el1, x0 +msr brbinf6_el1, x0 +msr brbinf7_el1, x0 +msr brbinf8_el1, x0 +msr brbinf9_el1, x0 +msr brbinf10_el1, x0 +msr brbinf11_el1, x0 +msr brbinf12_el1, x0 +msr brbinf13_el1, x0 +msr brbinf14_el1, x0 +msr brbinf15_el1, x0 +msr brbinf16_el1, x0 +msr brbinf17_el1, x0 +msr brbinf18_el1, x0 +msr brbinf19_el1, x0 +msr brbinf20_el1, x0 +msr brbinf21_el1, x0 +msr brbinf22_el1, x0 +msr brbinf23_el1, x0 +msr brbinf24_el1, x0 +msr brbinf25_el1, x0 +msr brbinf26_el1, x0 +msr brbinf27_el1, x0 +msr brbinf28_el1, x0 +msr brbinf29_el1, x0 +msr brbinf30_el1, x0 +msr brbinf31_el1, x0 diff --git a/gas/testsuite/gas/aarch64/brbe.d b/gas/testsuite/gas/aarch64/brbe.d new file mode 100644 index 00000000000..2a37f10cdf4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/brbe.d @@ -0,0 +1,113 @@ +#name: BRBE System registers +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + +[^:]+: d5319000 mrs x0, brbcr_el1 +[^:]+: d5359000 mrs x0, brbcr_el12 +[^:]+: d5319020 mrs x0, brbfcr_el1 +[^:]+: d5319040 mrs x0, brbts_el1 +[^:]+: d5319100 mrs x0, brbinfinj_el1 +[^:]+: d5319120 mrs x0, brbsrcinj_el1 +[^:]+: d5319140 mrs x0, brbtgtinj_el1 +[^:]+: d5319200 mrs x0, brbidr0_el1 +[^:]+: d5349000 mrs x0, brbcr_el2 +[^:]+: d5318020 mrs x0, brbsrc0_el1 +[^:]+: d5318a20 mrs x0, brbsrc10_el1 +[^:]+: d5318b20 mrs x0, brbsrc11_el1 +[^:]+: d5318c20 mrs x0, brbsrc12_el1 +[^:]+: d5318d20 mrs x0, brbsrc13_el1 +[^:]+: d5318e20 mrs x0, brbsrc14_el1 +[^:]+: d5318f20 mrs x0, brbsrc15_el1 +[^:]+: d53180a0 mrs x0, brbsrc16_el1 +[^:]+: d53181a0 mrs x0, brbsrc17_el1 +[^:]+: d53182a0 mrs x0, brbsrc18_el1 +[^:]+: d53183a0 mrs x0, brbsrc19_el1 +[^:]+: d53184a0 mrs x0, brbsrc20_el1 +[^:]+: d53185a0 mrs x0, brbsrc21_el1 +[^:]+: d53186a0 mrs x0, brbsrc22_el1 +[^:]+: d53187a0 mrs x0, brbsrc23_el1 +[^:]+: d53188a0 mrs x0, brbsrc24_el1 +[^:]+: d53189a0 mrs x0, brbsrc25_el1 +[^:]+: d5318aa0 mrs x0, brbsrc26_el1 +[^:]+: d5318ba0 mrs x0, brbsrc27_el1 +[^:]+: d5318ca0 mrs x0, brbsrc28_el1 +[^:]+: d5318da0 mrs x0, brbsrc29_el1 +[^:]+: d5318ea0 mrs x0, brbsrc30_el1 +[^:]+: d5318fa0 mrs x0, brbsrc31_el1 +[^:]+: d5318040 mrs x0, brbtgt0_el1 +[^:]+: d5318140 mrs x0, brbtgt1_el1 +[^:]+: d5318240 mrs x0, brbtgt2_el1 +[^:]+: d5318340 mrs x0, brbtgt3_el1 +[^:]+: d5318440 mrs x0, brbtgt4_el1 +[^:]+: d5318540 mrs x0, brbtgt5_el1 +[^:]+: d5318640 mrs x0, brbtgt6_el1 +[^:]+: d5318740 mrs x0, brbtgt7_el1 +[^:]+: d5318840 mrs x0, brbtgt8_el1 +[^:]+: d5318940 mrs x0, brbtgt9_el1 +[^:]+: d5318a40 mrs x0, brbtgt10_el1 +[^:]+: d5318b40 mrs x0, brbtgt11_el1 +[^:]+: d5318c40 mrs x0, brbtgt12_el1 +[^:]+: d5318d40 mrs x0, brbtgt13_el1 +[^:]+: d5318e40 mrs x0, brbtgt14_el1 +[^:]+: d5318f40 mrs x0, brbtgt15_el1 +[^:]+: d53180c0 mrs x0, brbtgt16_el1 +[^:]+: d53181c0 mrs x0, brbtgt17_el1 +[^:]+: d53182c0 mrs x0, brbtgt18_el1 +[^:]+: d53183c0 mrs x0, brbtgt19_el1 +[^:]+: d53184c0 mrs x0, brbtgt20_el1 +[^:]+: d53185c0 mrs x0, brbtgt21_el1 +[^:]+: d53186c0 mrs x0, brbtgt22_el1 +[^:]+: d53187c0 mrs x0, brbtgt23_el1 +[^:]+: d53188c0 mrs x0, brbtgt24_el1 +[^:]+: d53189c0 mrs x0, brbtgt25_el1 +[^:]+: d5318ac0 mrs x0, brbtgt26_el1 +[^:]+: d5318bc0 mrs x0, brbtgt27_el1 +[^:]+: d5318cc0 mrs x0, brbtgt28_el1 +[^:]+: d5318dc0 mrs x0, brbtgt29_el1 +[^:]+: d5318ec0 mrs x0, brbtgt30_el1 +[^:]+: d5318fc0 mrs x0, brbtgt31_el1 +[^:]+: d5318000 mrs x0, brbinf0_el1 +[^:]+: d5318100 mrs x0, brbinf1_el1 +[^:]+: d5318200 mrs x0, brbinf2_el1 +[^:]+: d5318300 mrs x0, brbinf3_el1 +[^:]+: d5318400 mrs x0, brbinf4_el1 +[^:]+: d5318500 mrs x0, brbinf5_el1 +[^:]+: d5318600 mrs x0, brbinf6_el1 +[^:]+: d5318700 mrs x0, brbinf7_el1 +[^:]+: d5318800 mrs x0, brbinf8_el1 +[^:]+: d5318900 mrs x0, brbinf9_el1 +[^:]+: d5318a00 mrs x0, brbinf10_el1 +[^:]+: d5318b00 mrs x0, brbinf11_el1 +[^:]+: d5318c00 mrs x0, brbinf12_el1 +[^:]+: d5318d00 mrs x0, brbinf13_el1 +[^:]+: d5318e00 mrs x0, brbinf14_el1 +[^:]+: d5318f00 mrs x0, brbinf15_el1 +[^:]+: d5318080 mrs x0, brbinf16_el1 +[^:]+: d5318180 mrs x0, brbinf17_el1 +[^:]+: d5318280 mrs x0, brbinf18_el1 +[^:]+: d5318380 mrs x0, brbinf19_el1 +[^:]+: d5318480 mrs x0, brbinf20_el1 +[^:]+: d5318580 mrs x0, brbinf21_el1 +[^:]+: d5318680 mrs x0, brbinf22_el1 +[^:]+: d5318780 mrs x0, brbinf23_el1 +[^:]+: d5318880 mrs x0, brbinf24_el1 +[^:]+: d5318980 mrs x0, brbinf25_el1 +[^:]+: d5318a80 mrs x0, brbinf26_el1 +[^:]+: d5318b80 mrs x0, brbinf27_el1 +[^:]+: d5318c80 mrs x0, brbinf28_el1 +[^:]+: d5318d80 mrs x0, brbinf29_el1 +[^:]+: d5318e80 mrs x0, brbinf30_el1 +[^:]+: d5318f80 mrs x0, brbinf31_el1 +[^:]+: d5119000 msr brbcr_el1, x0 +[^:]+: d5159000 msr brbcr_el12, x0 +[^:]+: d5119020 msr brbfcr_el1, x0 +[^:]+: d5119040 msr brbts_el1, x0 +[^:]+: d5119100 msr brbinfinj_el1, x0 +[^:]+: d5119120 msr brbsrcinj_el1, x0 +[^:]+: d5119140 msr brbtgtinj_el1, x0 +[^:]+: d5149000 msr brbcr_el2, x0 diff --git a/gas/testsuite/gas/aarch64/brbe.s b/gas/testsuite/gas/aarch64/brbe.s new file mode 100644 index 00000000000..c4e062de6f8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/brbe.s @@ -0,0 +1,109 @@ +/* Branch Record Buffer Extension system registers. */ + +/* Read from BRBE system registers. */ +mrs x0, brbcr_el1 +mrs x0, brbcr_el12 +mrs x0, brbfcr_el1 +mrs x0, brbts_el1 +mrs x0, brbinfinj_el1 +mrs x0, brbsrcinj_el1 +mrs x0, brbtgtinj_el1 +mrs x0, brbidr0_el1 +mrs x0, brbcr_el2 +mrs x0, brbsrc0_el1 +mrs x0, brbsrc10_el1 +mrs x0, brbsrc11_el1 +mrs x0, brbsrc12_el1 +mrs x0, brbsrc13_el1 +mrs x0, brbsrc14_el1 +mrs x0, brbsrc15_el1 +mrs x0, brbsrc16_el1 +mrs x0, brbsrc17_el1 +mrs x0, brbsrc18_el1 +mrs x0, brbsrc19_el1 +mrs x0, brbsrc20_el1 +mrs x0, brbsrc21_el1 +mrs x0, brbsrc22_el1 +mrs x0, brbsrc23_el1 +mrs x0, brbsrc24_el1 +mrs x0, brbsrc25_el1 +mrs x0, brbsrc26_el1 +mrs x0, brbsrc27_el1 +mrs x0, brbsrc28_el1 +mrs x0, brbsrc29_el1 +mrs x0, brbsrc30_el1 +mrs x0, brbsrc31_el1 +mrs x0, brbtgt0_el1 +mrs x0, brbtgt1_el1 +mrs x0, brbtgt2_el1 +mrs x0, brbtgt3_el1 +mrs x0, brbtgt4_el1 +mrs x0, brbtgt5_el1 +mrs x0, brbtgt6_el1 +mrs x0, brbtgt7_el1 +mrs x0, brbtgt8_el1 +mrs x0, brbtgt9_el1 +mrs x0, brbtgt10_el1 +mrs x0, brbtgt11_el1 +mrs x0, brbtgt12_el1 +mrs x0, brbtgt13_el1 +mrs x0, brbtgt14_el1 +mrs x0, brbtgt15_el1 +mrs x0, brbtgt16_el1 +mrs x0, brbtgt17_el1 +mrs x0, brbtgt18_el1 +mrs x0, brbtgt19_el1 +mrs x0, brbtgt20_el1 +mrs x0, brbtgt21_el1 +mrs x0, brbtgt22_el1 +mrs x0, brbtgt23_el1 +mrs x0, brbtgt24_el1 +mrs x0, brbtgt25_el1 +mrs x0, brbtgt26_el1 +mrs x0, brbtgt27_el1 +mrs x0, brbtgt28_el1 +mrs x0, brbtgt29_el1 +mrs x0, brbtgt30_el1 +mrs x0, brbtgt31_el1 +mrs x0, brbinf0_el1 +mrs x0, brbinf1_el1 +mrs x0, brbinf2_el1 +mrs x0, brbinf3_el1 +mrs x0, brbinf4_el1 +mrs x0, brbinf5_el1 +mrs x0, brbinf6_el1 +mrs x0, brbinf7_el1 +mrs x0, brbinf8_el1 +mrs x0, brbinf9_el1 +mrs x0, brbinf10_el1 +mrs x0, brbinf11_el1 +mrs x0, brbinf12_el1 +mrs x0, brbinf13_el1 +mrs x0, brbinf14_el1 +mrs x0, brbinf15_el1 +mrs x0, brbinf16_el1 +mrs x0, brbinf17_el1 +mrs x0, brbinf18_el1 +mrs x0, brbinf19_el1 +mrs x0, brbinf20_el1 +mrs x0, brbinf21_el1 +mrs x0, brbinf22_el1 +mrs x0, brbinf23_el1 +mrs x0, brbinf24_el1 +mrs x0, brbinf25_el1 +mrs x0, brbinf26_el1 +mrs x0, brbinf27_el1 +mrs x0, brbinf28_el1 +mrs x0, brbinf29_el1 +mrs x0, brbinf30_el1 +mrs x0, brbinf31_el1 + +/* Write to BRBE system registers. */ +msr brbcr_el1, x0 +msr brbcr_el12, x0 +msr brbfcr_el1, x0 +msr brbts_el1, x0 +msr brbinfinj_el1, x0 +msr brbsrcinj_el1, x0 +msr brbtgtinj_el1, x0 +msr brbcr_el2, x0 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index b97d05563f5..cebf8a45adb 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4554,6 +4554,112 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0), SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ), + SR_CORE ("brbcr_el1", CPENC (2,1,C9,C0,0), 0), + SR_CORE ("brbcr_el12", CPENC (2,5,C9,C0,0), 0), + SR_CORE ("brbfcr_el1", CPENC (2,1,C9,C0,1), 0), + SR_CORE ("brbts_el1", CPENC (2,1,C9,C0,2), 0), + SR_CORE ("brbinfinj_el1", CPENC (2,1,C9,C1,0), 0), + SR_CORE ("brbsrcinj_el1", CPENC (2,1,C9,C1,1), 0), + SR_CORE ("brbtgtinj_el1", CPENC (2,1,C9,C1,2), 0), + SR_CORE ("brbidr0_el1", CPENC (2,1,C9,C2,0), F_REG_READ), + SR_CORE ("brbcr_el2", CPENC (2,4,C9,C0,0), 0), + SR_CORE ("brbsrc0_el1", CPENC (2,1,C8,C0,1), F_REG_READ), + SR_CORE ("brbsrc1_el1", CPENC (2,1,C8,C1,1), F_REG_READ), + SR_CORE ("brbsrc2_el1", CPENC (2,1,C8,C2,1), F_REG_READ), + SR_CORE ("brbsrc3_el1", CPENC (2,1,C8,C3,1), F_REG_READ), + SR_CORE ("brbsrc4_el1", CPENC (2,1,C8,C4,1), F_REG_READ), + SR_CORE ("brbsrc5_el1", CPENC (2,1,C8,C5,1), F_REG_READ), + SR_CORE ("brbsrc6_el1", CPENC (2,1,C8,C6,1), F_REG_READ), + SR_CORE ("brbsrc7_el1", CPENC (2,1,C8,C7,1), F_REG_READ), + SR_CORE ("brbsrc8_el1", CPENC (2,1,C8,C8,1), F_REG_READ), + SR_CORE ("brbsrc9_el1", CPENC (2,1,C8,C9,1), F_REG_READ), + SR_CORE ("brbsrc10_el1", CPENC (2,1,C8,C10,1), F_REG_READ), + SR_CORE ("brbsrc11_el1", CPENC (2,1,C8,C11,1), F_REG_READ), + SR_CORE ("brbsrc12_el1", CPENC (2,1,C8,C12,1), F_REG_READ), + SR_CORE ("brbsrc13_el1", CPENC (2,1,C8,C13,1), F_REG_READ), + SR_CORE ("brbsrc14_el1", CPENC (2,1,C8,C14,1), F_REG_READ), + SR_CORE ("brbsrc15_el1", CPENC (2,1,C8,C15,1), F_REG_READ), + SR_CORE ("brbsrc16_el1", CPENC (2,1,C8,C0,5), F_REG_READ), + SR_CORE ("brbsrc17_el1", CPENC (2,1,C8,C1,5), F_REG_READ), + SR_CORE ("brbsrc18_el1", CPENC (2,1,C8,C2,5), F_REG_READ), + SR_CORE ("brbsrc19_el1", CPENC (2,1,C8,C3,5), F_REG_READ), + SR_CORE ("brbsrc20_el1", CPENC (2,1,C8,C4,5), F_REG_READ), + SR_CORE ("brbsrc21_el1", CPENC (2,1,C8,C5,5), F_REG_READ), + SR_CORE ("brbsrc22_el1", CPENC (2,1,C8,C6,5), F_REG_READ), + SR_CORE ("brbsrc23_el1", CPENC (2,1,C8,C7,5), F_REG_READ), + SR_CORE ("brbsrc24_el1", CPENC (2,1,C8,C8,5), F_REG_READ), + SR_CORE ("brbsrc25_el1", CPENC (2,1,C8,C9,5), F_REG_READ), + SR_CORE ("brbsrc26_el1", CPENC (2,1,C8,C10,5), F_REG_READ), + SR_CORE ("brbsrc27_el1", CPENC (2,1,C8,C11,5), F_REG_READ), + SR_CORE ("brbsrc28_el1", CPENC (2,1,C8,C12,5), F_REG_READ), + SR_CORE ("brbsrc29_el1", CPENC (2,1,C8,C13,5), F_REG_READ), + SR_CORE ("brbsrc30_el1", CPENC (2,1,C8,C14,5), F_REG_READ), + SR_CORE ("brbsrc31_el1", CPENC (2,1,C8,C15,5), F_REG_READ), + SR_CORE ("brbtgt0_el1", CPENC (2,1,C8,C0,2), F_REG_READ), + SR_CORE ("brbtgt1_el1", CPENC (2,1,C8,C1,2), F_REG_READ), + SR_CORE ("brbtgt2_el1", CPENC (2,1,C8,C2,2), F_REG_READ), + SR_CORE ("brbtgt3_el1", CPENC (2,1,C8,C3,2), F_REG_READ), + SR_CORE ("brbtgt4_el1", CPENC (2,1,C8,C4,2), F_REG_READ), + SR_CORE ("brbtgt5_el1", CPENC (2,1,C8,C5,2), F_REG_READ), + SR_CORE ("brbtgt6_el1", CPENC (2,1,C8,C6,2), F_REG_READ), + SR_CORE ("brbtgt7_el1", CPENC (2,1,C8,C7,2), F_REG_READ), + SR_CORE ("brbtgt8_el1", CPENC (2,1,C8,C8,2), F_REG_READ), + SR_CORE ("brbtgt9_el1", CPENC (2,1,C8,C9,2), F_REG_READ), + SR_CORE ("brbtgt10_el1", CPENC (2,1,C8,C10,2), F_REG_READ), + SR_CORE ("brbtgt11_el1", CPENC (2,1,C8,C11,2), F_REG_READ), + SR_CORE ("brbtgt12_el1", CPENC (2,1,C8,C12,2), F_REG_READ), + SR_CORE ("brbtgt13_el1", CPENC (2,1,C8,C13,2), F_REG_READ), + SR_CORE ("brbtgt14_el1", CPENC (2,1,C8,C14,2), F_REG_READ), + SR_CORE ("brbtgt15_el1", CPENC (2,1,C8,C15,2), F_REG_READ), + SR_CORE ("brbtgt16_el1", CPENC (2,1,C8,C0,6), F_REG_READ), + SR_CORE ("brbtgt17_el1", CPENC (2,1,C8,C1,6), F_REG_READ), + SR_CORE ("brbtgt18_el1", CPENC (2,1,C8,C2,6), F_REG_READ), + SR_CORE ("brbtgt19_el1", CPENC (2,1,C8,C3,6), F_REG_READ), + SR_CORE ("brbtgt20_el1", CPENC (2,1,C8,C4,6), F_REG_READ), + SR_CORE ("brbtgt21_el1", CPENC (2,1,C8,C5,6), F_REG_READ), + SR_CORE ("brbtgt22_el1", CPENC (2,1,C8,C6,6), F_REG_READ), + SR_CORE ("brbtgt23_el1", CPENC (2,1,C8,C7,6), F_REG_READ), + SR_CORE ("brbtgt24_el1", CPENC (2,1,C8,C8,6), F_REG_READ), + SR_CORE ("brbtgt25_el1", CPENC (2,1,C8,C9,6), F_REG_READ), + SR_CORE ("brbtgt26_el1", CPENC (2,1,C8,C10,6), F_REG_READ), + SR_CORE ("brbtgt27_el1", CPENC (2,1,C8,C11,6), F_REG_READ), + SR_CORE ("brbtgt28_el1", CPENC (2,1,C8,C12,6), F_REG_READ), + SR_CORE ("brbtgt29_el1", CPENC (2,1,C8,C13,6), F_REG_READ), + SR_CORE ("brbtgt30_el1", CPENC (2,1,C8,C14,6), F_REG_READ), + SR_CORE ("brbtgt31_el1", CPENC (2,1,C8,C15,6), F_REG_READ), + SR_CORE ("brbinf0_el1", CPENC (2,1,C8,C0,0), F_REG_READ), + SR_CORE ("brbinf1_el1", CPENC (2,1,C8,C1,0), F_REG_READ), + SR_CORE ("brbinf2_el1", CPENC (2,1,C8,C2,0), F_REG_READ), + SR_CORE ("brbinf3_el1", CPENC (2,1,C8,C3,0), F_REG_READ), + SR_CORE ("brbinf4_el1", CPENC (2,1,C8,C4,0), F_REG_READ), + SR_CORE ("brbinf5_el1", CPENC (2,1,C8,C5,0), F_REG_READ), + SR_CORE ("brbinf6_el1", CPENC (2,1,C8,C6,0), F_REG_READ), + SR_CORE ("brbinf7_el1", CPENC (2,1,C8,C7,0), F_REG_READ), + SR_CORE ("brbinf8_el1", CPENC (2,1,C8,C8,0), F_REG_READ), + SR_CORE ("brbinf9_el1", CPENC (2,1,C8,C9,0), F_REG_READ), + SR_CORE ("brbinf10_el1", CPENC (2,1,C8,C10,0), F_REG_READ), + SR_CORE ("brbinf11_el1", CPENC (2,1,C8,C11,0), F_REG_READ), + SR_CORE ("brbinf12_el1", CPENC (2,1,C8,C12,0), F_REG_READ), + SR_CORE ("brbinf13_el1", CPENC (2,1,C8,C13,0), F_REG_READ), + SR_CORE ("brbinf14_el1", CPENC (2,1,C8,C14,0), F_REG_READ), + SR_CORE ("brbinf15_el1", CPENC (2,1,C8,C15,0), F_REG_READ), + SR_CORE ("brbinf16_el1", CPENC (2,1,C8,C0,4), F_REG_READ), + SR_CORE ("brbinf17_el1", CPENC (2,1,C8,C1,4), F_REG_READ), + SR_CORE ("brbinf18_el1", CPENC (2,1,C8,C2,4), F_REG_READ), + SR_CORE ("brbinf19_el1", CPENC (2,1,C8,C3,4), F_REG_READ), + SR_CORE ("brbinf20_el1", CPENC (2,1,C8,C4,4), F_REG_READ), + SR_CORE ("brbinf21_el1", CPENC (2,1,C8,C5,4), F_REG_READ), + SR_CORE ("brbinf22_el1", CPENC (2,1,C8,C6,4), F_REG_READ), + SR_CORE ("brbinf23_el1", CPENC (2,1,C8,C7,4), F_REG_READ), + SR_CORE ("brbinf24_el1", CPENC (2,1,C8,C8,4), F_REG_READ), + SR_CORE ("brbinf25_el1", CPENC (2,1,C8,C9,4), F_REG_READ), + SR_CORE ("brbinf26_el1", CPENC (2,1,C8,C10,4), F_REG_READ), + SR_CORE ("brbinf27_el1", CPENC (2,1,C8,C11,4), F_REG_READ), + SR_CORE ("brbinf28_el1", CPENC (2,1,C8,C12,4), F_REG_READ), + SR_CORE ("brbinf29_el1", CPENC (2,1,C8,C13,4), F_REG_READ), + SR_CORE ("brbinf30_el1", CPENC (2,1,C8,C14,4), F_REG_READ), + SR_CORE ("brbinf31_el1", CPENC (2,1,C8,C15,4), F_REG_READ), + { 0, CPENC (0,0,0,0,0), 0, 0 } };