From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 11:06:19 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2386
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=627ae6f5f48f504588b72e10f080cc7a0bce9887;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 275cb0f1c..98cab5c46 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -473,6 +473,13 @@ all on a 3.5 watt budget at only 250 mhz in 130 nm.  Yet to take
 proper advantage of its capability required an astounding 5-10
 *days* per line of assembly code. 20 lines of optimised
 Assembler taking six months to write can in no way be termed
-"productive".
+"productive", yet this extreme level of unproductivity is an inherent
+side-effect of going down the parallel-processing rabbithole.
 
 **In short, we are in "Programmer's nightmare" territory**
+
+Having dug a proverbial hole that rivals the Grand Canyon, and
+jumped in it feet-first, the next
+task is to piece together a strategy to climb back out and show
+how falling back in can be avoided. This takes some explaining,
+and requires some background on various historical research efforts