From: Kito Cheng Date: Sun, 13 May 2018 17:18:31 +0000 (+0000) Subject: [NDS32] Implment n15 pipeline. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=628332f85dbcd0996f68afae47b2b6d134b7b268;p=gcc.git [NDS32] Implment n15 pipeline. gcc/ * config.gcc (nds32*-*-*): Check that n15 is valid to --with-cpu. * config/nds32/nds32-graywolf.md: New file. * config/nds32/nds32-opts.h (nds32_cpu_type): Add CPU_GRAYWOLF. * config/nds32/nds32-pipelines-auxiliary.c: Implementation for n15 pipeline. * config/nds32/nds32-protos.h: More declarations for n15 pipeline. * config/nds32/nds32-utils.c: More implementations for n15 pipeline. * config/nds32/nds32.md (pipeline_model): Add graywolf. * config/nds32/nds32.opt (mcpu): Support n15 pipeline cpus. * config/nds32/pipelines.md: Include n15 settings. Co-Authored-By: Chung-Ju Wu From-SVN: r260214 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9fdc34558da..4901cb1fd07 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2018-05-13 Kito Cheng + Chung-Ju Wu + + * config.gcc (nds32*-*-*): Check that n15 is valid to --with-cpu. + * config/nds32/nds32-graywolf.md: New file. + * config/nds32/nds32-opts.h (nds32_cpu_type): Add CPU_GRAYWOLF. + * config/nds32/nds32-pipelines-auxiliary.c: Implementation for n15 + pipeline. + * config/nds32/nds32-protos.h: More declarations for n15 pipeline. + * config/nds32/nds32-utils.c: More implementations for n15 pipeline. + * config/nds32/nds32.md (pipeline_model): Add graywolf. + * config/nds32/nds32.opt (mcpu): Support n15 pipeline cpus. + * config/nds32/pipelines.md: Include n15 settings. + 2018-05-13 Kito Cheng Chung-Ju Wu diff --git a/gcc/config.gcc b/gcc/config.gcc index c8eda1dbc69..be43a09e8af 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4367,11 +4367,11 @@ case "${target}" in "") with_cpu=n9 ;; - n6 | n7 |n8 | e8 | s8 | n9 | n10 | d10 | n12 | n13) + n6 | n7 |n8 | e8 | s8 | n9 | n10 | d10 | n12 | n13 | n15) # OK ;; *) - echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9 n10 d10 n12 n13" 1>&2 + echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9 n10 d10 n12 n13 n15" 1>&2 exit 1 ;; esac diff --git a/gcc/config/nds32/nds32-graywolf.md b/gcc/config/nds32/nds32-graywolf.md new file mode 100644 index 00000000000..f0c98a6f75d --- /dev/null +++ b/gcc/config/nds32/nds32-graywolf.md @@ -0,0 +1,471 @@ +;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler +;; Copyright (C) 2012-2013 Free Software Foundation, Inc. +;; Contributed by Andes Technology Corporation. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; ------------------------------------------------------------------------ +;; Define Graywolf pipeline settings. +;; ------------------------------------------------------------------------ + +(define_automaton "nds32_graywolf_machine") + +(define_cpu_unit "gw_ii_0" "nds32_graywolf_machine") +(define_cpu_unit "gw_ii_1" "nds32_graywolf_machine") +(define_cpu_unit "gw_ex_p0" "nds32_graywolf_machine") +(define_cpu_unit "gw_mm_p0" "nds32_graywolf_machine") +(define_cpu_unit "gw_wb_p0" "nds32_graywolf_machine") +(define_cpu_unit "gw_ex_p1" "nds32_graywolf_machine") +(define_cpu_unit "gw_mm_p1" "nds32_graywolf_machine") +(define_cpu_unit "gw_wb_p1" "nds32_graywolf_machine") +(define_cpu_unit "gw_iq_p2" "nds32_graywolf_machine") +(define_cpu_unit "gw_rf_p2" "nds32_graywolf_machine") +(define_cpu_unit "gw_e1_p2" "nds32_graywolf_machine") +(define_cpu_unit "gw_e2_p2" "nds32_graywolf_machine") +(define_cpu_unit "gw_e3_p2" "nds32_graywolf_machine") +(define_cpu_unit "gw_e4_p2" "nds32_graywolf_machine") + +(define_reservation "gw_ii" "gw_ii_0 | gw_ii_1") +(define_reservation "gw_ex" "gw_ex_p0 | gw_ex_p1") +(define_reservation "gw_mm" "gw_mm_p0 | gw_mm_p1") +(define_reservation "gw_wb" "gw_wb_p0 | gw_wb_p1") + +(define_reservation "gw_ii_all" "gw_ii_0 + gw_ii_1") + +(define_insn_reservation "nds_gw_unknown" 1 + (and (eq_attr "type" "unknown") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ex, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_misc" 1 + (and (eq_attr "type" "misc") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ex, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_mmu" 1 + (and (eq_attr "type" "mmu") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ex, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_alu" 1 + (and (and (eq_attr "type" "alu") + (match_test "!nds32::movd44_insn_p (insn)")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ex, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_movd44" 1 + (and (and (eq_attr "type" "alu") + (match_test "nds32::movd44_insn_p (insn)")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_alu_shift" 1 + (and (eq_attr "type" "alu_shift") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ex*2, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_pbsad" 1 + (and (eq_attr "type" "pbsad") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ex*3, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_pbsada" 1 + (and (eq_attr "type" "pbsada") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ex*3, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_load" 1 + (and (and (eq_attr "type" "load") + (match_test "!nds32::post_update_insn_p (insn)")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_2w" 1 + (and (and (eq_attr "type" "load") + (match_test "nds32::post_update_insn_p (insn)")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_all, gw_ex_p1, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store" 1 + (and (and (eq_attr "type" "store") + (match_test "!nds32::store_offset_reg_p (insn)")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_3r" 1 + (and (and (eq_attr "type" "store") + (match_test "nds32::store_offset_reg_p (insn)")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_all, gw_ex_p1, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_1" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "1")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_2" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "2")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*2, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_3" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "3")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*3, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_4" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "4")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_5" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "5")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_6" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "6")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_7" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "7")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_8" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "8")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_load_multiple_12" 1 + (and (and (eq_attr "type" "load_multiple") + (eq_attr "combo" "12")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_1" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "1")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_2" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "2")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*2, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_3" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "3")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*3, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_4" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "4")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_5" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "5")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_6" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "6")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_7" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "7")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_8" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "8")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_store_multiple_12" 1 + (and (and (eq_attr "type" "store_multiple") + (eq_attr "combo" "12")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_1, gw_ex_p1*4, gw_mm_p1, gw_wb_p1") + +(define_insn_reservation "nds_gw_mul_fast1" 1 + (and (match_test "nds32_mul_config == MUL_TYPE_FAST_1") + (and (eq_attr "type" "mul") + (eq_attr "pipeline_model" "graywolf"))) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_mul_fast2" 1 + (and (match_test "nds32_mul_config == MUL_TYPE_FAST_2") + (and (eq_attr "type" "mul") + (eq_attr "pipeline_model" "graywolf"))) + "gw_ii_0, gw_ex_p0*2, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_mul_slow" 1 + (and (match_test "nds32_mul_config == MUL_TYPE_SLOW") + (and (eq_attr "type" "mul") + (eq_attr "pipeline_model" "graywolf"))) + "gw_ii_0, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_mac_fast1" 1 + (and (match_test "nds32_mul_config == MUL_TYPE_FAST_1") + (and (eq_attr "type" "mac") + (eq_attr "pipeline_model" "graywolf"))) + "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_mac_fast2" 1 + (and (match_test "nds32_mul_config == MUL_TYPE_FAST_2") + (and (eq_attr "type" "mac") + (eq_attr "pipeline_model" "graywolf"))) + "gw_ii_all, gw_ex_p0*2, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_mac_slow" 1 + (and (match_test "nds32_mul_config == MUL_TYPE_SLOW") + (and (eq_attr "type" "mac") + (eq_attr "pipeline_model" "graywolf"))) + "gw_ii_all, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_div" 1 + (and (and (eq_attr "type" "div") + (match_test "!nds32::divmod_p (insn)")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_div_2w" 1 + (and (and (eq_attr "type" "div") + (match_test "nds32::divmod_p (insn)")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_all, gw_ex_p0*4, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_branch" 1 + (and (eq_attr "type" "branch") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_alu" 1 + (and (eq_attr "type" "dalu") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ex, gw_mm, gw_wb") + +(define_insn_reservation "nds_gw_dsp_alu64" 1 + (and (eq_attr "type" "dalu64") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_alu_round" 1 + (and (eq_attr "type" "daluround") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_cmp" 1 + (and (eq_attr "type" "dcmp") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_clip" 1 + (and (eq_attr "type" "dclip") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_mul" 1 + (and (eq_attr "type" "dmul") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_mac" 1 + (and (eq_attr "type" "dmac") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_insb" 1 + (and (eq_attr "type" "dinsb") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_pack" 1 + (and (eq_attr "type" "dpack") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_bpick" 1 + (and (eq_attr "type" "dbpick") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_0, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_dsp_wext" 1 + (and (eq_attr "type" "dwext") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii_all, gw_ex_p0, gw_mm_p0, gw_wb_p0") + +(define_insn_reservation "nds_gw_fpu_alu" 4 + (and (eq_attr "type" "falu") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_muls" 4 + (and (eq_attr "type" "fmuls") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_muld" 4 + (and (eq_attr "type" "fmuld") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*2, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_macs" 4 + (and (eq_attr "type" "fmacs") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*3, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_macd" 4 + (and (eq_attr "type" "fmacd") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*4, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_divs" 4 + (and (ior (eq_attr "type" "fdivs") + (eq_attr "type" "fsqrts")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*14, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_divd" 4 + (and (ior (eq_attr "type" "fdivd") + (eq_attr "type" "fsqrtd")) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2*28, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_fast_alu" 2 + (and (ior (eq_attr "type" "fcmp") + (ior (eq_attr "type" "fabs") + (ior (eq_attr "type" "fcpy") + (eq_attr "type" "fcmov")))) + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_fmtsr" 1 + (and (eq_attr "type" "fmtsr") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_fmtdr" 1 + (and (eq_attr "type" "fmtdr") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ii+gw_iq_p2, gw_iq_p2+gw_rf_p2, gw_rf_p2+gw_e1_p2, gw_e1_p2+gw_e2_p2, gw_e2_p2+gw_e3_p2, gw_e3_p2+gw_e4_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_fmfsr" 1 + (and (eq_attr "type" "fmfsr") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_fmfdr" 1 + (and (eq_attr "type" "fmfdr") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_ii+gw_iq_p2, gw_iq_p2+gw_rf_p2, gw_rf_p2+gw_e1_p2, gw_e1_p2+gw_e2_p2, gw_e2_p2+gw_e3_p2, gw_e3_p2+gw_e4_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_load" 3 + (and (eq_attr "type" "fload") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") + +(define_insn_reservation "nds_gw_fpu_store" 1 + (and (eq_attr "type" "fstore") + (eq_attr "pipeline_model" "graywolf")) + "gw_ii, gw_iq_p2, gw_rf_p2, gw_e1_p2, gw_e2_p2, gw_e3_p2, gw_e4_p2") + +;; FPU_ADDR_OUT -> FPU_ADDR_IN +;; Main pipeline rules don't need this because those default latency is 1. +(define_bypass 1 + "nds_gw_fpu_load, nds_gw_fpu_store" + "nds_gw_fpu_load, nds_gw_fpu_store" + "nds32_gw_ex_to_ex_p" +) + +;; LD, MUL, MAC, DIV, DALU64, DMUL, DMAC, DALUROUND, DBPICK, DWEXT +;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU, +;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb +(define_bypass 2 + "nds_gw_load, nds_gw_load_2w,\ + nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ + nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ + nds_gw_div, nds_gw_div_2w,\ + nds_gw_dsp_alu64, nds_gw_dsp_mul, nds_gw_dsp_mac,\ + nds_gw_dsp_alu_round, nds_gw_dsp_bpick, nds_gw_dsp_wext" + "nds_gw_alu, nds_gw_movd44, nds_gw_alu_shift,\ + nds_gw_pbsad, nds_gw_pbsada,\ + nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ + nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ + nds_gw_branch,\ + nds_gw_div, nds_gw_div_2w,\ + nds_gw_load, nds_gw_load_2w, nds_gw_store, nds_gw_store_3r,\ + nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ + nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ + nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12,\ + nds_gw_store_multiple_1,nds_gw_store_multiple_2, nds_gw_store_multiple_3,\ + nds_gw_store_multiple_4,nds_gw_store_multiple_5, nds_gw_store_multiple_6,\ + nds_gw_store_multiple_7,nds_gw_store_multiple_8, nds_gw_store_multiple_12,\ + nds_gw_mmu,\ + nds_gw_dsp_alu, nds_gw_dsp_alu_round,\ + nds_gw_dsp_mul, nds_gw_dsp_mac, nds_gw_dsp_pack,\ + nds_gw_dsp_insb, nds_gw_dsp_cmp, nds_gw_dsp_clip,\ + nds_gw_dsp_wext, nds_gw_dsp_bpick" + "nds32_gw_mm_to_ex_p" +) + +;; LMW(N, N) +;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU +;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb +(define_bypass 2 + "nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ + nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ + nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12" + "nds_gw_alu, nds_gw_movd44, nds_gw_alu_shift,\ + nds_gw_pbsad, nds_gw_pbsada,\ + nds_gw_mul_fast1, nds_gw_mul_fast2, nds_gw_mul_slow,\ + nds_gw_mac_fast1, nds_gw_mac_fast2, nds_gw_mac_slow,\ + nds_gw_branch,\ + nds_gw_div, nds_gw_div_2w,\ + nds_gw_load, nds_gw_load_2w, nds_gw_store, nds_gw_store_3r,\ + nds_gw_load_multiple_1,nds_gw_load_multiple_2, nds_gw_load_multiple_3,\ + nds_gw_load_multiple_4,nds_gw_load_multiple_5, nds_gw_load_multiple_6,\ + nds_gw_load_multiple_7,nds_gw_load_multiple_8, nds_gw_load_multiple_12,\ + nds_gw_store_multiple_1,nds_gw_store_multiple_2, nds_gw_store_multiple_3,\ + nds_gw_store_multiple_4,nds_gw_store_multiple_5, nds_gw_store_multiple_6,\ + nds_gw_store_multiple_7,nds_gw_store_multiple_8, nds_gw_store_multiple_12,\ + nds_gw_mmu,\ + nds_gw_dsp_alu, nds_gw_dsp_alu_round,\ + nds_gw_dsp_mul, nds_gw_dsp_mac, nds_gw_dsp_pack,\ + nds_gw_dsp_insb, nds_gw_dsp_cmp, nds_gw_dsp_clip,\ + nds_gw_dsp_wext, nds_gw_dsp_bpick" + "nds32_gw_last_load_to_ex_p" +) diff --git a/gcc/config/nds32/nds32-opts.h b/gcc/config/nds32/nds32-opts.h index 3c853e4f164..e0400655757 100644 --- a/gcc/config/nds32/nds32-opts.h +++ b/gcc/config/nds32/nds32-opts.h @@ -43,6 +43,7 @@ enum nds32_cpu_type CPU_E8, CPU_N9, CPU_N10, + CPU_GRAYWOLF, CPU_N12, CPU_N13, CPU_SIMPLE diff --git a/gcc/config/nds32/nds32-pipelines-auxiliary.c b/gcc/config/nds32/nds32-pipelines-auxiliary.c index 560137c248f..53619d22510 100644 --- a/gcc/config/nds32/nds32-pipelines-auxiliary.c +++ b/gcc/config/nds32/nds32-pipelines-auxiliary.c @@ -931,6 +931,88 @@ n10_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg) return false; } +/* Check the dependency between the producer defining DEF_REG and CONSUMER + requiring input operand at EX. */ +bool +gw_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg) +{ + rtx use_rtx; + + switch (get_attr_type (consumer)) + { + case TYPE_ALU: + case TYPE_PBSAD: + case TYPE_MUL: + case TYPE_DALU: + case TYPE_DALU64: + case TYPE_DMUL: + case TYPE_DPACK: + case TYPE_DINSB: + case TYPE_DCMP: + case TYPE_DCLIP: + case TYPE_DALUROUND: + use_rtx = SET_SRC (PATTERN (consumer)); + break; + + case TYPE_ALU_SHIFT: + use_rtx = extract_shift_reg (consumer); + break; + + case TYPE_PBSADA: + return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg); + + case TYPE_MAC: + case TYPE_DMAC: + use_rtx = extract_mac_non_acc_rtx (consumer); + break; + + /* Some special instructions, divmodsi4 and udivmodsi4, produce two + results, the quotient and the remainder. We have to check the + dependency from the producer to the first micro-operation. */ + case TYPE_DIV: + if (divmod_p (consumer)) + use_rtx = SET_SRC (parallel_element (consumer, 0)); + else + use_rtx = SET_SRC (PATTERN (consumer)); + break; + + case TYPE_DWEXT: + return wext_odd_dep_p (consumer, def_reg); + + case TYPE_DBPICK: + return bpick_ra_rb_dep_p (consumer, def_reg); + + case TYPE_MMU: + if (GET_CODE (PATTERN (consumer)) == SET) + use_rtx = SET_SRC (PATTERN (consumer)); + else + return true; + break; + + case TYPE_LOAD: + case TYPE_STORE: + use_rtx = extract_mem_rtx (consumer); + break; + + case TYPE_LOAD_MULTIPLE: + case TYPE_STORE_MULTIPLE: + use_rtx = extract_base_reg (consumer); + break; + + case TYPE_BRANCH: + use_rtx = PATTERN (consumer); + break; + + default: + gcc_unreachable (); + } + + if (reg_overlap_p (def_reg, use_rtx)) + return true; + + return false; +} + /* Check dependencies from any stages to ALU_E1 (E1). This is a helper function of n13_consumed_by_e1_dep_p (). */ bool @@ -1532,6 +1614,67 @@ nds32_n10_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer) return n10_consumed_by_ex_dep_p (consumer, last_def_reg); } +/* Guard functions for Graywolf cores. */ + +/* Check dependencies from EX to EX (ADDR_OUT -> ADDR_IN). */ +bool +nds32_gw_ex_to_ex_p (rtx_insn *producer, rtx_insn *consumer) +{ + return nds32_n10_ex_to_ex_p (producer, consumer); +} + +/* Check dependencies from MM to EX. */ +bool +nds32_gw_mm_to_ex_p (rtx_insn *producer, rtx_insn *consumer) +{ + rtx def_reg; + + switch (get_attr_type (producer)) + { + case TYPE_LOAD: + case TYPE_MUL: + case TYPE_MAC: + case TYPE_DALU64: + case TYPE_DMUL: + case TYPE_DMAC: + case TYPE_DALUROUND: + case TYPE_DBPICK: + case TYPE_DWEXT: + def_reg = SET_DEST (PATTERN (producer)); + break; + + /* Some special instructions, divmodsi4 and udivmodsi4, produce two + results, the quotient and the remainder. We have to handle them + individually. */ + case TYPE_DIV: + if (divmod_p (producer)) + { + rtx def_reg1 = SET_DEST (parallel_element (producer, 0)); + rtx def_reg2 = SET_DEST (parallel_element (producer, 1)); + + return (gw_consumed_by_ex_dep_p (consumer, def_reg1) + || gw_consumed_by_ex_dep_p (consumer, def_reg2)); + } + + def_reg = SET_DEST (PATTERN (producer)); + break; + + default: + gcc_unreachable (); + } + + return gw_consumed_by_ex_dep_p (consumer, def_reg); +} + +/* Check dependencies from LMW(N, N) to EX. */ +bool +nds32_gw_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer) +{ + rtx last_def_reg = extract_nth_access_reg (producer, -1); + + return gw_consumed_by_ex_dep_p (consumer, last_def_reg); +} + /* Guard functions for N12/N13 cores. */ /* Check dependencies from E2 to E1. */ diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h index 9debad3a6a6..a7d679e01f0 100644 --- a/gcc/config/nds32/nds32-protos.h +++ b/gcc/config/nds32/nds32-protos.h @@ -125,6 +125,10 @@ extern bool nds32_n10_ex_to_ex_p (rtx_insn *, rtx_insn *); extern bool nds32_n10_mm_to_ex_p (rtx_insn *, rtx_insn *); extern bool nds32_n10_last_load_to_ex_p (rtx_insn *, rtx_insn *); +extern bool nds32_gw_ex_to_ex_p (rtx_insn *, rtx_insn *); +extern bool nds32_gw_mm_to_ex_p (rtx_insn *, rtx_insn *); +extern bool nds32_gw_last_load_to_ex_p (rtx_insn *, rtx_insn *); + extern bool nds32_n13_e2_to_e1_p (rtx_insn *, rtx_insn *); extern bool nds32_n13_load_to_e1_p (rtx_insn *, rtx_insn *); extern bool nds32_n13_load_to_e2_p (rtx_insn *, rtx_insn *); @@ -297,11 +301,13 @@ bool load_single_p (rtx_insn *); bool store_single_p (rtx_insn *); bool load_double_p (rtx_insn *); bool store_double_p (rtx_insn *); +bool store_offset_reg_p (rtx_insn *); bool post_update_insn_p (rtx_insn *); bool immed_offset_p (rtx); int find_post_update_rtx (rtx_insn *); rtx extract_mem_rtx (rtx_insn *); rtx extract_base_reg (rtx_insn *); +rtx extract_offset_rtx (rtx_insn *); rtx extract_shift_reg (rtx); diff --git a/gcc/config/nds32/nds32-utils.c b/gcc/config/nds32/nds32-utils.c index 6c93774c453..7c93cd2edd0 100644 --- a/gcc/config/nds32/nds32-utils.c +++ b/gcc/config/nds32/nds32-utils.c @@ -142,6 +142,23 @@ store_double_p (rtx_insn *insn) return true; } +bool +store_offset_reg_p (rtx_insn *insn) +{ + if (get_attr_type (insn) != TYPE_STORE) + return false; + + rtx offset_rtx = extract_offset_rtx (insn); + + if (offset_rtx == NULL_RTX) + return false; + + if (REG_P (offset_rtx)) + return true; + + return false; +} + /* Determine if INSN is a post update insn. */ bool post_update_insn_p (rtx_insn *insn) @@ -316,22 +333,114 @@ extract_base_reg (rtx_insn *insn) if (REG_P (XEXP (mem_rtx, 0))) return XEXP (mem_rtx, 0); + /* (mem (lo_sum (reg) (symbol_ref)) */ + if (GET_CODE (XEXP (mem_rtx, 0)) == LO_SUM) + return XEXP (XEXP (mem_rtx, 0), 0); + plus_rtx = XEXP (mem_rtx, 0); if (GET_CODE (plus_rtx) == SYMBOL_REF || GET_CODE (plus_rtx) == CONST) return NULL_RTX; - gcc_assert (GET_CODE (plus_rtx) == PLUS - || GET_CODE (plus_rtx) == POST_INC - || GET_CODE (plus_rtx) == POST_DEC - || GET_CODE (plus_rtx) == POST_MODIFY); - gcc_assert (REG_P (XEXP (plus_rtx, 0))); /* (mem (plus (reg) (const_int))) or + (mem (plus (mult (reg) (const_int 4)) (reg))) or (mem (post_inc (reg))) or (mem (post_dec (reg))) or (mem (post_modify (reg) (plus (reg) (reg)))) */ - return XEXP (plus_rtx, 0); + gcc_assert (GET_CODE (plus_rtx) == PLUS + || GET_CODE (plus_rtx) == POST_INC + || GET_CODE (plus_rtx) == POST_DEC + || GET_CODE (plus_rtx) == POST_MODIFY); + + if (REG_P (XEXP (plus_rtx, 0))) + return XEXP (plus_rtx, 0); + + gcc_assert (REG_P (XEXP (plus_rtx, 1))); + return XEXP (plus_rtx, 1); +} + +/* Extract the offset rtx from load/store insns. The function returns + NULL_RTX if offset is absent. */ +rtx +extract_offset_rtx (rtx_insn *insn) +{ + rtx mem_rtx; + rtx plus_rtx; + rtx offset_rtx; + + /* Find the MEM rtx. The multiple load/store insns doens't have + the offset field so we can return NULL_RTX here. */ + switch (get_attr_type (insn)) + { + case TYPE_LOAD_MULTIPLE: + case TYPE_STORE_MULTIPLE: + return NULL_RTX; + + case TYPE_LOAD: + case TYPE_FLOAD: + case TYPE_STORE: + case TYPE_FSTORE: + mem_rtx = extract_mem_rtx (insn); + break; + + default: + gcc_unreachable (); + } + + gcc_assert (MEM_P (mem_rtx)); + + /* (mem (reg)) */ + if (REG_P (XEXP (mem_rtx, 0))) + return NULL_RTX; + + plus_rtx = XEXP (mem_rtx, 0); + + switch (GET_CODE (plus_rtx)) + { + case SYMBOL_REF: + case CONST: + case POST_INC: + case POST_DEC: + return NULL_RTX; + + case PLUS: + /* (mem (plus (reg) (const_int))) or + (mem (plus (mult (reg) (const_int 4)) (reg))) */ + if (REG_P (XEXP (plus_rtx, 0))) + offset_rtx = XEXP (plus_rtx, 1); + else + { + gcc_assert (REG_P (XEXP (plus_rtx, 1))); + offset_rtx = XEXP (plus_rtx, 0); + } + + if (ARITHMETIC_P (offset_rtx)) + { + gcc_assert (GET_CODE (offset_rtx) == MULT); + gcc_assert (REG_P (XEXP (offset_rtx, 0))); + offset_rtx = XEXP (offset_rtx, 0); + } + break; + + case LO_SUM: + /* (mem (lo_sum (reg) (symbol_ref)) */ + offset_rtx = XEXP (plus_rtx, 1); + break; + + case POST_MODIFY: + /* (mem (post_modify (reg) (plus (reg) (reg / const_int)))) */ + gcc_assert (REG_P (XEXP (plus_rtx, 0))); + plus_rtx = XEXP (plus_rtx, 1); + gcc_assert (GET_CODE (plus_rtx) == PLUS); + offset_rtx = XEXP (plus_rtx, 0); + break; + + default: + gcc_unreachable (); + } + + return offset_rtx; } /* Extract the register of the shift operand from an ALU_SHIFT rtx. */ diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 0c1f301e483..6379212550e 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -56,13 +56,14 @@ ;; ------------------------------------------------------------------------ ;; CPU pipeline model. -(define_attr "pipeline_model" "n7,n8,e8,n9,n10,n13,simple" +(define_attr "pipeline_model" "n7,n8,e8,n9,n10,graywolf,n13,simple" (const (cond [(match_test "nds32_cpu_option == CPU_N7") (const_string "n7") (match_test "nds32_cpu_option == CPU_E8") (const_string "e8") (match_test "nds32_cpu_option == CPU_N6 || nds32_cpu_option == CPU_N8") (const_string "n8") (match_test "nds32_cpu_option == CPU_N9") (const_string "n9") (match_test "nds32_cpu_option == CPU_N10") (const_string "n10") + (match_test "nds32_cpu_option == CPU_GRAYWOLF") (const_string "graywolf") (match_test "nds32_cpu_option == CPU_N12") (const_string "n13") (match_test "nds32_cpu_option == CPU_N13") (const_string "n13") (match_test "nds32_cpu_option == CPU_SIMPLE") (const_string "simple")] diff --git a/gcc/config/nds32/nds32.opt b/gcc/config/nds32/nds32.opt index f69bddc1b38..f1c1bf91895 100644 --- a/gcc/config/nds32/nds32.opt +++ b/gcc/config/nds32/nds32.opt @@ -287,6 +287,27 @@ Enum(nds32_cpu_type) String(d1088-fpu) Value(CPU_N10) EnumValue Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10) +EnumValue +Enum(nds32_cpu_type) Undocumented String(graywolf) Value(CPU_GRAYWOLF) + +EnumValue +Enum(nds32_cpu_type) String(n15) Value(CPU_GRAYWOLF) + +EnumValue +Enum(nds32_cpu_type) String(d15) Value(CPU_GRAYWOLF) + +EnumValue +Enum(nds32_cpu_type) String(n15s) Value(CPU_GRAYWOLF) + +EnumValue +Enum(nds32_cpu_type) String(d15s) Value(CPU_GRAYWOLF) + +EnumValue +Enum(nds32_cpu_type) String(n15f) Value(CPU_GRAYWOLF) + +EnumValue +Enum(nds32_cpu_type) String(d15f) Value(CPU_GRAYWOLF) + EnumValue Enum(nds32_cpu_type) String(n12) Value(CPU_N12) diff --git a/gcc/config/nds32/pipelines.md b/gcc/config/nds32/pipelines.md index 29514aef777..12cd2623f1c 100644 --- a/gcc/config/nds32/pipelines.md +++ b/gcc/config/nds32/pipelines.md @@ -49,6 +49,12 @@ (include "nds32-n10.md") +;; ------------------------------------------------------------------------ +;; Include Graywolf pipeline settings. +;; ------------------------------------------------------------------------ +(include "nds32-graywolf.md") + + ;; ------------------------------------------------------------------------ ;; Include N12/N13 pipeline settings. ;; ------------------------------------------------------------------------