From: whitequark <whitequark@whitequark.org>
Date: Mon, 8 Jul 2019 15:11:29 +0000 (+0000)
Subject: verilog_backend: dump attributes on SwitchRule.
X-Git-Tag: working-ls180~1217^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=628437b01cd37b95c020b2f4c4e2f2d8f0e9bf8b;p=yosys.git

verilog_backend: dump attributes on SwitchRule.

This appears to be an omission.
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 18c92521f..6288502a5 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1494,6 +1494,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		return;
 	}
 
+	dump_attributes(f, indent, sw->attributes);
 	f << stringf("%s" "casez (", indent.c_str());
 	dump_sigspec(f, sw->signal);
 	f << stringf(")\n");