From: James Greenhalgh <james.greenhalgh@arm.com>
Date: Wed, 18 May 2016 08:00:33 +0000 (+0000)
Subject: [Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=628d13d9995e6b1d2c0847106ebf2645b3884875;p=gcc.git

[Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence

gcc/

	* config/aarch64/aarch64-simd.md
	(aarch64_reduc_plus_internal<mode>): Rename to...
	(reduc_plus_scal): ...This, and remove previous implementation.

From-SVN: r236360
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 61a485c0923..e71ce6d75b5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-05-18  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64-simd.md
+	(aarch64_reduc_plus_internal<mode>): Rename to...
+	(reduc_plus_scal): ...This, and remove previous implementation.
+
 2016-05-18  Richard Biener  <rguenther@suse.de>
 
 	* passes.def: Put late dse and cd_dce in canonical order.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 17b89452e0b..59a578f5937 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1979,19 +1979,6 @@
   }
 )
 
-(define_expand "reduc_plus_scal_<mode>"
-  [(match_operand:<VEL> 0 "register_operand" "=w")
-   (match_operand:V2F 1 "register_operand" "w")]
-  "TARGET_SIMD"
-  {
-    rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0));
-    rtx scratch = gen_reg_rtx (<MODE>mode);
-    emit_insn (gen_aarch64_reduc_plus_internal<mode> (scratch, operands[1]));
-    emit_insn (gen_aarch64_get_lane<mode> (operands[0], scratch, elt));
-    DONE;
-  }
-)
-
 (define_insn "aarch64_reduc_plus_internal<mode>"
  [(set (match_operand:VDQV 0 "register_operand" "=w")
        (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")]
@@ -2010,9 +1997,9 @@
   [(set_attr "type" "neon_reduc_add")]
 )
 
-(define_insn "aarch64_reduc_plus_internal<mode>"
- [(set (match_operand:V2F 0 "register_operand" "=w")
-       (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
+(define_insn "reduc_plus_scal_<mode>"
+ [(set (match_operand:<VEL> 0 "register_operand" "=w")
+       (unspec:<VEL> [(match_operand:V2F 1 "register_operand" "w")]
 		   UNSPEC_FADDV))]
  "TARGET_SIMD"
  "faddp\\t%<Vetype>0, %1.<Vtype>"