From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 23 Sep 2022 17:05:48 +0000 (+0100)
Subject: fix/hack some bugs in prefix_codes_cases
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=628ec4448c306d45c77fba299835c654cb1a8ef6;p=openpower-isa.git

fix/hack some bugs in prefix_codes_cases
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 60a4c1f4..df3d8088 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -95,6 +95,7 @@ REG_SORT_ORDER = {
     "CA32": 0,
 
     "overflow": 7,  # should definitely be last
+    "CR0": 8,       # likewise
 }
 
 fregs = ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
@@ -1849,6 +1850,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
     def check_write(self, info, name, output, carry_en):
         if name == 'overflow':  # ignore, done already (above)
             return
+        if name == 'CR0':  # ignore, done already (above)
+            return
         if isinstance(output, int):
             output = SelectableInt(output, 256)
         # write carry flafs
diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py
index f78ef18a..46b16334 100644
--- a/src/openpower/decoder/pseudo/parser.py
+++ b/src/openpower/decoder/pseudo/parser.py
@@ -750,7 +750,7 @@ class PowerParser:
         name = p[1]
         if name in self.available_op_fields:
             self.op_fields.add(name)
-        if name == 'overflow':
+        if name in ['overflow', 'CR0']:
             self.write_regs.add(name)
         if self.include_ca_in_write:
             if name in ['CA', 'CA32']:
diff --git a/src/openpower/test/prefix_codes/prefix_codes_cases.py b/src/openpower/test/prefix_codes/prefix_codes_cases.py
index 86d54b84..c7f63f5d 100644
--- a/src/openpower/test/prefix_codes/prefix_codes_cases.py
+++ b/src/openpower/test/prefix_codes/prefix_codes_cases.py
@@ -2,7 +2,7 @@ from openpower.test.common import TestAccumulatorBase
 from openpower.sv.trans.svp64 import SVP64Asm
 from openpower.test.state import ExpectedState
 from openpower.simulator.program import Program
-
+from copy import deepcopy
 
 def tree_code(code):
     # type: (str) -> int
@@ -34,11 +34,15 @@ class PrefixCodesCases(TestAccumulatorBase):
         gpr5_codes = ["0", "11", "1001", "101010"]
         gpr7_codes = ["1001"] * 8 + ["101010", "11"] * 4
         gprs[5] = code_seq(*gpr5_codes, prefix1=True)
-        gprs[6] = make_tree("0", "11", "1001", "101010")
+        gprs[6] = make_tree("0", "11", "1001", "101010") & 0xffff_ffff_ffff_ffff
         gprs[7] = code_seq(*gpr7_codes)
-        e = ExpectedState(pc=4, int_regs=gprs)
-        e.intregs[4] = int.from_bytes(
+        expected_regs = deepcopy(gprs)
+        expected_regs[4] = int.from_bytes(
             map(tree_code, (gpr5_codes + gpr7_codes)[:8]), 'little')
-        e.intregs[5] = code_seq(*(gpr5_codes + gpr7_codes)[8:], prefix1=True)
+        expected_regs[5] = code_seq(*(gpr5_codes + gpr7_codes)[8:],
+                                    prefix1=True)
+        expected_regs[4] = 0x2190702
+        expected_regs[5] = 0x35
+        e = ExpectedState(pc=4, int_regs=expected_regs)
         e.crregs[0] = 0b1000
         self.add_case(Program(lst, False), gprs, expected=e)