From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 Mar 2019 19:49:07 +0000 (+0000)
Subject: reduce FPNormModSingle setup to input connections
X-Git-Tag: ls180-24jan2020~1560
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=62a4243b7f48b91f0228ee40a31bb8010cf58ac8;p=ieee754fpu.git

reduce FPNormModSingle setup to input connections
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index dd095e24..f89f4d63 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -1026,15 +1026,12 @@ class FPNorm1ModSingle:
     def ospec(self):
         return FPNorm1Data(self.width, self.id_wid)
 
-    def setup(self, m, i, out_z):
+    def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.normalise_1 = self
-
         m.d.comb += self.i.eq(i)
 
-        m.d.comb += out_z.eq(self.o.z)
-
     def elaborate(self, platform):
         m = Module()
 
@@ -1265,9 +1262,9 @@ class FPNormToPack(FPState, FPID):
 
         # Normalisation (chained to input in_z+in_of)
         nmod = FPNorm1ModSingle(self.width, self.id_wid)
+        nmod.setup(m, i)
         n_out = nmod.ospec()
-        nmod.setup(m, i, n_out.z)
-        m.d.comb += n_out.roundz.eq(nmod.o.roundz)
+        m.d.comb += n_out.eq(nmod.o)
 
         # Rounding (chained to normalisation)
         rmod = FPRoundMod(self.width, self.id_wid)