From: lkcl <lkcl@web>
Date: Sat, 19 Aug 2023 16:10:05 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=62bd89d4731af2826437d06637a9692eba085671;p=libreriscv.git

---

diff --git a/HDL_workflow/HyperRAM.mdwn b/HDL_workflow/HyperRAM.mdwn
index f18bc289a..b41f4548d 100644
--- a/HDL_workflow/HyperRAM.mdwn
+++ b/HDL_workflow/HyperRAM.mdwn
@@ -10,6 +10,8 @@
 * Winbond Verilog Model for W956A8MBY:
   <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
 * [[shakti/m_class/HyperRAM]]
+* <https://github.com/icebreaker-fpga/icebreaker-pmod/tree/master/quadhyperram>
+* <https://hackaday.io/project/168594-feather-wing-pmod-adapter> <https://github.com/TomKeddie/prj-pmod-feather>
 
 ```
 from nmigen.resources.memory import HyperRAMResources