From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 16 May 2020 15:19:21 +0000 (-0400)
Subject: Consolidate every pipe_data to use alu's integer data
X-Git-Tag: div_pipeline~1138
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=62cf6457bad0098c8601354a50664753a12eff06;p=soc.git

Consolidate every pipe_data to use alu's integer data
---

diff --git a/src/soc/alu/pipe_data.py b/src/soc/alu/pipe_data.py
index 13be9747..c386397a 100644
--- a/src/soc/alu/pipe_data.py
+++ b/src/soc/alu/pipe_data.py
@@ -16,6 +16,9 @@ class IntegerData:
     def eq(self, i):
         return [self.ctx.eq(i.ctx)]
 
+    def ports(self):
+        return self.ctx.ports()
+
 
 class ALUInputData(IntegerData):
     def __init__(self, pspec):
diff --git a/src/soc/branch/pipe_data.py b/src/soc/branch/pipe_data.py
index 3d3b9afb..351ca5ec 100644
--- a/src/soc/branch/pipe_data.py
+++ b/src/soc/branch/pipe_data.py
@@ -32,20 +32,9 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.decoder.power_decoder2 import Data
+from soc.alu.pipe_data import IntegerData
 
 
-class IntegerData:
-
-    def __init__(self, pspec):
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def __iter__(self):
-        yield from self.ctx
-
-    def eq(self, i):
-        return [self.ctx.eq(i.ctx)]
-
 class BranchInputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
diff --git a/src/soc/cr/pipe_data.py b/src/soc/cr/pipe_data.py
index bb248c23..d56c8f3f 100644
--- a/src/soc/cr/pipe_data.py
+++ b/src/soc/cr/pipe_data.py
@@ -1,18 +1,6 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
-
-
-class IntegerData:
-
-    def __init__(self, pspec):
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def __iter__(self):
-        yield from self.ctx
-
-    def eq(self, i):
-        return [self.ctx.eq(i.ctx)]
+from soc.alu.pipe_data import IntegerData
 
 
 class CRInputData(IntegerData):
diff --git a/src/soc/logical/pipe_data.py b/src/soc/logical/pipe_data.py
index 34d9c0ae..4bf064fe 100644
--- a/src/soc/logical/pipe_data.py
+++ b/src/soc/logical/pipe_data.py
@@ -1,18 +1,6 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
-
-
-class IntegerData:
-
-    def __init__(self, pspec):
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def __iter__(self):
-        yield from self.ctx
-
-    def eq(self, i):
-        return [self.ctx.eq(i.ctx)]
+from soc.alu.pipe_data import IntegerData
 
 
 class ALUInputData(IntegerData):
diff --git a/src/soc/shift_rot/pipe_data.py b/src/soc/shift_rot/pipe_data.py
index 291ecf0a..7f98d16b 100644
--- a/src/soc/shift_rot/pipe_data.py
+++ b/src/soc/shift_rot/pipe_data.py
@@ -2,19 +2,7 @@ from nmigen import Signal, Const
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.alu.alu_input_record import CompALUOpSubset
 from ieee754.fpcommon.getop import FPPipeContext
-
-
-class IntegerData:
-
-    def __init__(self, pspec):
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def __iter__(self):
-        yield from self.ctx
-
-    def eq(self, i):
-        return [self.ctx.eq(i.ctx)]
+from soc.alu.pipe_data import IntegerData
 
 
 class ShiftRotInputData(IntegerData):