From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 20 Feb 2019 00:06:03 +0000 (-0800)
Subject: abc9 to cope with indexed wires when creating $lut from $_NOT_
X-Git-Tag: working-ls180~1237^2~300
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=62e5ff9ba8ce9711317f97efdb9810491aaa4f06;p=yosys.git

abc9 to cope with indexed wires when creating $lut from $_NOT_
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index f63b69acd..e85cf48e1 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -597,7 +597,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 							// Otherwise, clone the driving LUT to guarantee that we
 							// won't increase the max logic depth
 							// (TODO: Optimise by not cloning unless will increase depth)
-							RTLIL::Cell* driver = mapped_mod->cell(stringf("%s_lut", a_bit.wire->name.c_str()));
+							RTLIL::IdString driver_name;
+							if (GetSize(a_bit.wire) == 1)
+								driver_name = stringf("%s_lut", a_bit.wire->name.c_str());
+							else
+								driver_name = stringf("%s[%d]_lut", a_bit.wire->name.c_str(), a_bit.offset);
+							RTLIL::Cell* driver = mapped_mod->cell(driver_name);
 							log_assert(driver);
 							auto driver_a = driver->getPort("\\A").chunks();
 							for (auto &chunk : driver_a)