From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 13 Apr 2022 10:11:57 +0000 (+0100)
Subject: get microwatt-verilator sim running at different boot base
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=62ea8451b596a5c53dc7421f1b1ce7b859453f70;p=ls2.git

get microwatt-verilator sim running at different boot base
and confirm working with hello_world recompiled to a different coldboot
start address
---

diff --git a/Makefile b/Makefile
index a41fe72..bfcb0c4 100644
--- a/Makefile
+++ b/Makefile
@@ -26,8 +26,8 @@ endif
 
 # Hello world
 MEMORY_SIZE=8192
-#RAM_INIT_FILE=hello_world/hello_world.bin
-RAM_INIT_FILE=coldboot/coldboot.bin
+RAM_INIT_FILE=hello_world/hello_world.bin
+#RAM_INIT_FILE=coldboot/coldboot.bin
 SIM_MAIN_BRAM=false
 
 # Micropython
@@ -58,6 +58,7 @@ microwatt-verilator: ls2.v \
                      verilator/microwatt-verilator.cpp \
                      verilator/uart-verilator.c
 	verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
+	-DDATA_BUS_WIDTH_8 \
     --assert \
 	--top-module top \
     --cc ls2.v \
diff --git a/hello_world/Makefile b/hello_world/Makefile
index 180f7b9..e1d6c98 100644
--- a/hello_world/Makefile
+++ b/hello_world/Makefile
@@ -5,8 +5,8 @@ ifneq ("$(ARCH)", "ppc64le")
 endif
 endif
 
-BOOT_INIT_BASE ?= 0xf0000000 # at QSPI address
-# BOOT_INIT_BASE ?= 0xff000000   # at ROM hi address (with coldboot firmware)
+#BOOT_INIT_BASE ?= 0xf0000000 # at QSPI address
+ BOOT_INIT_BASE ?= 0xff000000   # at ROM hi address (with coldboot firmware)
 # BOOT_INIT_BASE ?= 0x0        # start at zero (usual)
 
 CC = $(CROSS_COMPILE)gcc
@@ -32,6 +32,7 @@ console.o: ../lib/console.c
 
 hello_world.elf: hello_world.o head.o console.o powerpc.lds
 	$(LD) $(LDFLAGS) -o $@ hello_world.o head.o console.o 
+	powerpc64le-linux-gnu-objdump -D hello_world.elf > hello_world.as
 
 hello_world.bin: hello_world.elf
 	$(OBJCOPY) -O binary $^ $@
@@ -40,7 +41,7 @@ hello_world.hex: hello_world.bin
 	../scripts/bin2hex.py $^ > $@
 
 clean:
-	@rm -f *.o hello_world.elf hello_world.bin hello_world.hex
+	@rm -f *.o hello_world.elf hello_world.bin hello_world.hex powerpc.lds
 distclean: clean
 	rm -f *~
 
diff --git a/src/ls2.py b/src/ls2.py
index df67247..708673b 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -366,7 +366,7 @@ class DDR3SoC(SoC, Elaboratable):
         """
 
         # DRAM Module
-        if ddr_pins is not None or fpga == 'sim':
+        if ddr_pins is not None: # or fpga == 'sim':
             ddrmodule = dram_cls(clk_freq, "1:2") # match DDR3 ASIC P/N
 
             #drs = lambda x: x