From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 12 Jan 2015 11:44:18 +0000 (+0100)
Subject: use new submodules/specials/clock_domains automatic collection
X-Git-Tag: 24jan2021_ls180~2572^2~61
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=62f55e32cf8f7e39a0462ad4133f7ac63b762fcb;p=litex.git

use new submodules/specials/clock_domains automatic collection
---

diff --git a/lib/sata/phy/k7/crg.py b/lib/sata/phy/k7/crg.py
index 8b47b342..3d008a67 100644
--- a/lib/sata/phy/k7/crg.py
+++ b/lib/sata/phy/k7/crg.py
@@ -8,8 +8,8 @@ class K7SATAPHYCRG(Module):
 		self.reset = Signal()
 		self.ready = Signal()
 
-		self.clock_domains.cd_sata_tx = ClockDomain()
-		self.clock_domains.cd_sata_rx = ClockDomain()
+		self.cd_sata_tx = ClockDomain()
+		self.cd_sata_rx = ClockDomain()
 
 	# CPLL
 		# (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps
diff --git a/lib/sata/test/phy_datapath_tb.py b/lib/sata/test/phy_datapath_tb.py
index f195e561..d91092f1 100644
--- a/lib/sata/test/phy_datapath_tb.py
+++ b/lib/sata/test/phy_datapath_tb.py
@@ -45,8 +45,8 @@ class CTRL(Module):
 class TB(Module):
 	def __init__(self):
 		# use sys_clk for each clock_domain
-		self.clock_domains.cd_sata_rx = ClockDomain()
-		self.clock_domains.cd_sata_tx = ClockDomain()
+		self.cd_sata_rx = ClockDomain()
+		self.cd_sata_tx = ClockDomain()
 		self.comb += [
 			self.cd_sata_rx.clk.eq(ClockSignal()),
 			self.cd_sata_rx.rst.eq(ResetSignal()),
diff --git a/targets/test.py b/targets/test.py
index ee38e0d0..850086ee 100644
--- a/targets/test.py
+++ b/targets/test.py
@@ -19,8 +19,8 @@ from migen.genlib.cdc import *
 
 class _CRG(Module):
 	def __init__(self, platform):
-		self.clock_domains.cd_sys = ClockDomain()
-		self.clock_domains.cd_por = ClockDomain(reset_less=True)
+		self.cd_sys = ClockDomain()
+		self.cd_por = ClockDomain(reset_less=True)
 
 		clk200 = platform.request("clk200")
 		clk200_se = Signal()