From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 1 Sep 2014 14:36:04 +0000 (+0200)
Subject: Added $alu support to test_cell
X-Git-Tag: yosys-0.4~177
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=630befdf6d58ab5f7c4ca1ea77c86df7b88ee259;p=yosys.git

Added $alu support to test_cell
---

diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 7f9f1f9b8..7c7d6b7fd 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -95,6 +95,27 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		cell->setPort("\\Y", wire);
 	}
 
+	if (cell_type == "$alu")
+	{
+		wire = module->addWire("\\CI");
+		wire->port_input = true;
+		cell->setPort("\\CI", wire);
+
+		wire = module->addWire("\\BI");
+		wire->port_input = true;
+		cell->setPort("\\BI", wire);
+
+		wire = module->addWire("\\X");
+		wire->width = SIZE(cell->getPort("\\Y"));
+		wire->port_output = true;
+		cell->setPort("\\X", wire);
+
+		wire = module->addWire("\\CO");
+		wire->width = SIZE(cell->getPort("\\Y"));
+		wire->port_output = true;
+		cell->setPort("\\CO", wire);
+	}
+
 	module->fixup_ports();
 	cell->fixup_parameters();
 	cell->check();
@@ -317,7 +338,7 @@ struct TestCellPass : public Pass {
 		// cell_types["$assert"] = "A";
 
 		cell_types["$lut"] = "*";
-		// cell_types["$alu"] = "*";
+		cell_types["$alu"] = "ABSY";
 
 		for (; argidx < SIZE(args); argidx++)
 		{