From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 15 Sep 2023 21:21:00 +0000 (-0700)
Subject: fix PowerDecoder2 to properly decode scalar EXTRA2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=630dfa6c8b6633d66d1a41368dfad927754846ed;p=openpower-isa.git

fix PowerDecoder2 to properly decode scalar EXTRA2

https://bugs.libre-soc.org/show_bug.cgi?id=1161
---

diff --git a/src/openpower/decoder/power_svp64_extra.py b/src/openpower/decoder/power_svp64_extra.py
index c956eb99..620f0660 100644
--- a/src/openpower/decoder/power_svp64_extra.py
+++ b/src/openpower/decoder/power_svp64_extra.py
@@ -105,8 +105,11 @@ class SVP64RegExtra(SVP64ExtraSpec):
         with m.If(self.isvec):
             # Vector: shifted up, extra in LSBs (RA << 2) | spec[1:2]
             comb += self.reg_out.eq(Cat(spec_aug, self.reg_in))
-        with m.Else():
-            # Scalar: not shifted up, extra in MSBs RA | (spec[1:2] << 5)
+        with m.Elif(self.etype == SVEType.EXTRA2):
+            # Scalar EXTRA2: not shifted up, extra in MSBs RA | (spec[1] << 5)
+            comb += self.reg_out.eq(Cat(self.reg_in, spec_aug[1]))
+        with m.Elif(self.etype == SVEType.EXTRA3):
+            # Scalar EXTRA3: not shifted up, extra in MSBs RA | (spec[1:2] << 5)
             comb += self.reg_out.eq(Cat(self.reg_in, spec_aug))
 
         return m