From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 28 May 2023 22:04:55 +0000 (+0300)
Subject: ppc/svp64: support divmod2du instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=631274f2b4e38dd8ee57ef1bcdd736246b7c2a70;p=binutils-gdb.git

ppc/svp64: support divmod2du instruction
---

diff --git a/gas/testsuite/gas/ppc/divmod2du.d b/gas/testsuite/gas/ppc/divmod2du.d
new file mode 100644
index 00000000000..d5b0ba34b98
--- /dev/null
+++ b/gas/testsuite/gas/ppc/divmod2du.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:\s+(13 e0 00 32|32 00 e0 13)\s+maddedu\sr31,r0,r0,r0
+.*:\s+(10 1f 00 32|32 00 1f 10)\s+maddedu\sr0,r31,r0,r0
+.*:\s+(10 00 f8 32|32 f8 00 10)\s+maddedu\sr0,r0,r31,r0
+.*:\s+(10 00 07 f2|f2 07 00 10)\s+maddedu\sr0,r0,r0,r31
+.*:\s+(13 e0 00 3a|3a 00 e0 13)\s+divmod2du\sr31,r0,r0,r0
+.*:\s+(10 1f 00 3a|3a 00 1f 10)\s+divmod2du\sr0,r31,r0,r0
+.*:\s+(10 00 f8 3a|3a f8 00 10)\s+divmod2du\sr0,r0,r31,r0
+.*:\s+(10 00 07 fa|fa 07 00 10)\s+divmod2du\sr0,r0,r0,r31
diff --git a/gas/testsuite/gas/ppc/divmod2du.s b/gas/testsuite/gas/ppc/divmod2du.s
new file mode 100644
index 00000000000..9ff3c24628c
--- /dev/null
+++ b/gas/testsuite/gas/ppc/divmod2du.s
@@ -0,0 +1,8 @@
+maddedu 31,0,0,0
+maddedu 0,31,0,0
+maddedu 0,0,31,0
+maddedu 0,0,0,31
+divmod2du 31,0,0,0
+divmod2du 0,31,0,0
+divmod2du 0,0,31,0
+divmod2du 0,0,0,31
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 4f3ab6a5949..dabde01e0ef 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -169,3 +169,4 @@ run_dump_test "absd"
 run_dump_test "bmask"
 run_dump_test "fptrans"
 run_dump_test "maddedu"
+run_dump_test "divmod2du"
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index a26b9dd96c3..23385cc24a1 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -5248,6 +5248,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ps_mul.",	A  (4,	25,1),	AFRB_MASK,   PPCPS,	0,		{FRT, FRA, FRC}},
 {"maddedu",	VXA(4,	50),	VXA_MASK,    SVP64,	PPCVLE,		{RT, RA, RB, RC}},
 {"maddld",	VXA(4,	51),	VXA_MASK,    POWER9,	0,		{RT, RA, RB, RC}},
+{"divmod2du",	VXA(4,	58),	VXA_MASK,    SFFS,	0,		{RT, RA, RB, RC}},
 {"ps_rsqrte",	A  (4,	26,0), AFRAFRC_MASK, PPCPS,	0,		{FRT, FRB}},
 {"ps_rsqrte.",	A  (4,	26,1), AFRAFRC_MASK, PPCPS,	0,		{FRT, FRB}},
 {"ps_msub",	A  (4,	28,0),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},