From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 07:38:49 +0000 (-0800)
Subject: Fix wire width
X-Git-Tag: working-ls180~778^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6318e3ce6df2484c4cc17856608e2a6354cd643a;p=yosys.git

Fix wire width
---

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index f50556d76..a0a3f2da5 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -1,8 +1,8 @@
 read_verilog <<EOT
-module top(input a, output [1:0] b);
+module top(input a, output b);
 wire c;
 (* submod="bar" *) sub s1(a, c);
-assign b[0] = c;
+assign b = c;
 endmodule
 
 module sub(input a, output c);