From: whitequark <whitequark@whitequark.org>
Date: Mon, 15 Apr 2019 14:29:46 +0000 (+0000)
Subject: README: fix some incorrect quoting.
X-Git-Tag: yosys-0.9~199^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6323e73cc94627125a275b22b0b8ea290e750bc3;p=yosys.git

README: fix some incorrect quoting.
---

diff --git a/README.md b/README.md
index 4048ecbc7..d000c5d63 100644
--- a/README.md
+++ b/README.md
@@ -312,10 +312,10 @@ Verilog Attributes and non-standard features
   passes to identify input and output ports of cells. The Verilog backend
   also does not output blackbox modules on default.
 
-- The ``dynports'' attribute is used by the Verilog front-end to mark modules
+- The ``dynports`` attribute is used by the Verilog front-end to mark modules
   that have ports with a width that depends on a parameter.
 
-- The ``hdlname'' attribute is used by some passes to document the original
+- The ``hdlname`` attribute is used by some passes to document the original
   (HDL) name of a module when renaming a module.
 
 - The ``keep`` attribute on cells and wires is used to mark objects that should