From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 15 Aug 2020 21:33:25 +0000 (+0100)
Subject: clear compalu data latch always on issue
X-Git-Tag: semi_working_ecp5~333
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6338d667387cc5fac8dd39bc6edfa43aff06c22c;p=soc.git

clear compalu data latch always on issue
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index c4dcfd15..79d4ccd1 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -276,7 +276,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
             wrok.append(ok & self.busy_o)
             with m.If(alu_pulse):
                 m.d.sync += data_r.eq(lro)
-            with m.Elif(self.issue_i):
+            with m.If(self.issue_i):
                 m.d.sync += data_r.eq(0)
             drl.append(data_r)