From: whitequark <cz@m-labs.hk>
Date: Mon, 17 Dec 2018 15:50:43 +0000 (+0000)
Subject: back.rtlil: update for Yosys master.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=633b1fbf7a80164bd4d1e0aef565686fac85cd44;p=nmigen.git

back.rtlil: update for Yosys master.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 6737130..70b9596 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -451,9 +451,7 @@ class _RHSValueCompiler(_ValueCompiler):
             raise TypeError # :nocov:
 
     def _prepare_value_for_Slice(self, value):
-        # Uncomment after the following is merged: https://github.com/YosysHQ/yosys/pull/741
-        # if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
-        if isinstance(value, ast.Signal):
+        if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
             sigspec = self(value)
         else:
             sigspec = self.s.rtlil.wire(len(value))