From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Thu, 5 Oct 2023 14:51:50 +0000 (+0100)
Subject: Corrected accidential indentation errors in special registers alterted
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=634b686acfa5c7fd596d2983a7c89cdaac875dbd;p=openpower-isa.git

Corrected accidential indentation errors in special registers alterted
---

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index 3fc3fec8..94c419e3 100644
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -80,7 +80,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -106,7 +106,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -176,7 +176,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -202,7 +202,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -272,7 +272,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -298,7 +298,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None