From: lkcl <lkcl@web>
Date: Sun, 17 Apr 2022 10:28:05 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2763
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63608204491b20fe6f953dddac71140b31e5a455;p=libreriscv.git

---

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 394cbf53a..e0aa2a14f 100644
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -32,7 +32,9 @@ FP instructions: useful for testing <http://weitz.de/ieee/>
 * [[isa/fparith]]
 * [[isa/fpcvt]]
 
-Variants only available under the [[sv/svp64]] namespace
+Variants only available under the [[sv/svp64]] namespace, these are
+all **DRAFT FORM**. Explanation of the rules for twin register targets
+(implicit RS, FRS) explained in SVPY4 [[sv/svp64/appendix]]
 
 * [[isa/svfixedload]]
 * [[isa/svfixedarith]]