From: lkcl Date: Sat, 25 Mar 2023 20:06:37 +0000 (+0000) Subject: (no commit message) X-Git-Tag: opf_rfc_ls001_v3~67 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6369ba4a40b61d66778b7962920fb14f96f3ce5a;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn index 8102fdb51..408578598 100644 --- a/openpower/sv/rfc/ls008.mdwn +++ b/openpower/sv/rfc/ls008.mdwn @@ -183,11 +183,11 @@ The format of the SVSTATE SPR is as follows: | 21:27 | dststep | for dststep = 0..VL-1 | | 28:29 | dsubstep | for substep = 0..SUBVL-1 | | 30:31 | ssubstep | for substep = 0..SUBVL-1 | -| 32:33 | mi0 | REMAP RA SVSHAPE0-3 | -| 34:35 | mi1 | REMAP RB SVSHAPE0-3 | -| 36:37 | mi2 | REMAP RC SVSHAPE0-3 | -| 38:39 | mo0 | REMAP RT SVSHAPE0-3 | -| 40:41 | mo1 | REMAP EA SVSHAPE0-3 | +| 32:33 | mi0 | REMAP RA/FRA/BFA SVSHAPE0-3 | +| 34:35 | mi1 | REMAP RB/FRB/BFB SVSHAPE0-3 | +| 36:37 | mi2 | REMAP RC/FRT SVSHAPE0-3 | +| 38:39 | mo0 | REMAP RT/FRT/BF SVSHAPE0-3 | +| 40:41 | mo1 | REMAP EA/RS/FRS SVSHAPE0-3 | | 42:46 | SVme | REMAP enable (RA-RT) | | 47:52 | rsvd | reserved | | 53 | pack | PACK (srcstrp reorder) | @@ -234,10 +234,13 @@ SVSTATE contains (and permits setting of): hardware **MUST** perform this many elements in parallel per instruction. Set to zero to indicate "no hint". * SVme - REMAP enable bits, indicating which register is to be - REMAPed. RA, RB, RC, RT or EA. -* mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4 + REMAPed: RA, RB, RC, RT and EA are the canonical (typical) register names + associated with each bit, with RA being the LSB and EA being the MSB. + See table below for ordering. When `SVme` is zero (0b00000) REMAP + is **fully disabled and inactive**. +* mi0-mi2/mo0-mo1 - when the corresponding SVme bit is enabled, these indicate the SVSHAPE (0-3) that the corresponding register (RA etc) - should use. + should use, as long as the register's corresponding SVme bit is set Programmer's Note: when REMAP is activated it becomes necessary on any context-switch (Interrupt or Function call) to detect (or know in advance)