From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sun, 10 May 2020 23:16:17 +0000 (-0400)
Subject: Actually implement rlwimi
X-Git-Tag: div_pipeline~1288
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6373958df521fbd5354da77c58c5ca93072674e8;p=soc.git

Actually implement rlwimi
---

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 59c896a5..9d8133f1 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -141,7 +141,7 @@ class ALUMainStage(PipeModBase):
                 comb += maskgen.mb.eq(mb+32)
                 comb += maskgen.me.eq(me+32)
                 comb += mask.eq(maskgen.o)
-                comb += self.o.o.eq(rotl_out & mask)
+                comb += self.o.o.eq((rotl_out & mask) | (self.i.b & ~mask))
                 
 
         ###### sticky overflow and context, both pass-through #####