From: Andreas Hansson <andreas.hansson@arm.com>
Date: Mon, 13 Feb 2012 11:45:11 +0000 (-0500)
Subject: MEM: Pass the ports from Python to C++ using the Swig params
X-Git-Tag: stable_2012_06_28~233
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63777fb23f043012ba052fc9c5968da7bdd59221;p=gem5.git

MEM: Pass the ports from Python to C++ using the Swig params

This patch adds basic information about the ports in the parameter
classes to be passed from the Python world to the corresponding C++
object. Currently, the only information passed is the number of
connected peers, which for a Port is either 0 or 1, and for a
VectorPort reflects the size of the VectorPort. The default port of
the bus had to be renamed to avoid using the name "default" as a field
in the parameter class. It is possible to extend the Swig'ed
information further and add e.g. a pair with a description and size.
---

diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index afdd84fe3..78138b083 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2004-2006 The Regents of The University of Michigan
 # Copyright (c) 2010 Advanced Micro Devices, Inc.
 # All rights reserved.
@@ -27,6 +39,7 @@
 #
 # Authors: Steve Reinhardt
 #          Nathan Binkert
+#          Andreas Hansson
 
 import sys
 from types import FunctionType, MethodType, ModuleType
@@ -386,6 +399,7 @@ class MetaSimObject(type):
         # will also be inherited from the base class's param struct
         # here).
         params = cls._params.local.values()
+        ports = cls._ports.local
 
         code('%module(package="m5.internal") param_$cls')
         code()
@@ -441,6 +455,7 @@ class MetaSimObject(type):
         # will also be inherited from the base class's param struct
         # here).
         params = cls._params.local.values()
+        ports = cls._ports.local
         try:
             ptypes = [p.ptype for p in params]
         except:
@@ -481,6 +496,8 @@ class EventQueue;
 ''')
         for param in params:
             param.cxx_predecls(code)
+        for port in ports.itervalues():
+            port.cxx_predecls(code)
         code()
 
         if cls._base:
@@ -517,6 +534,9 @@ class EventQueue;
             ''')
         for param in params:
             param.cxx_decl(code)
+        for port in ports.itervalues():
+            port.cxx_decl(code)
+
         code.dedent()
         code('};')
 
@@ -960,7 +980,8 @@ class SimObject(object):
         for port_name in port_names:
             port = self._port_refs.get(port_name, None)
             if port != None:
-                setattr(cc_params, port_name, port)
+                setattr(cc_params, 'port_' + port_name + '_connection_count',
+                        len(port))
         self._ccParams = cc_params
         return self._ccParams
 
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 95958e3e6..0a369e641 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1349,6 +1349,11 @@ class PortRef(object):
     def __str__(self):
         return '%s.%s' % (self.simobj, self.name)
 
+    def __len__(self):
+        # Return the number of connected ports, i.e. 0 is we have no
+        # peer and 1 if we do.
+        return int(self.peer != None)
+
     # for config.ini, print peer's name (not ours)
     def ini_str(self):
         return str(self.peer)
@@ -1462,6 +1467,11 @@ class VectorPortRef(object):
     def __str__(self):
         return '%s.%s[:]' % (self.simobj, self.name)
 
+    def __len__(self):
+        # Return the number of connected peers, corresponding the the
+        # length of the elements.
+        return len(self.elements)
+
     # for config.ini, print peer's name (not ours)
     def ini_str(self):
         return ' '.join([el.ini_str() for el in self.elements])
@@ -1525,6 +1535,17 @@ class Port(object):
     def connect(self, simobj, ref):
         self.makeRef(simobj).connect(ref)
 
+    # No need for any pre-declarations at the moment as we merely rely
+    # on an unsigned int.
+    def cxx_predecls(self, code):
+        pass
+
+    # Declare an unsigned int with the same name as the port, that
+    # will eventually hold the number of connected ports (and thus the
+    # number of elements for a VectorPort).
+    def cxx_decl(self, code):
+        code('unsigned int port_${{self.name}}_connection_count;')
+
 class MasterPort(Port):
     # MasterPort("description")
     def __init__(self, *args):